Difference: JRichTBTrigger (13 vs. 14)

Revision 142018-10-21 - StephenWotton

Line: 1 to 1


Line: 102 to 102


The JRichTBTrigger register map can be viewed here. \ No newline at end of file

New timing trigger TB2018

GUI installed in richtbuser account on lbrichtb.

Run it with

cd ~richtbuser/Public/Java/Trigger2Kit
java -Djava.library.path=. -jar JRichTBTrigger.jar

Requires external clock (from miniDAQ/muDAQ) connected to Y12/W12.

Set pulse widths to 10 (100ns). Set deadtime to 5 (500ns) or greater.

Firmware is not loaded permanently into flash. On power cycle, reload the firmware as follows (stop the trigger GUI first):

cd ~richtbuser/Public/Java/JAVAKIT
java -Djava.library.path=. -jar XilinxDjtg.jar

  • Click OK to connect to the trigger board.
  • Click Choose file to select the firmware.
  • Click Load FPGA to program the FPGA.
  • Exit program when done.

Use firmware richtbtrigger-x4-v3.bin.

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