Difference: RichPdmdb (1 vs. 32)

Revision 322019-09-02 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 146 to 146
 

Inventory

Changed:
<
<
The web pages are generated from XML data and are more authoritative. The Excel files are convenient for sorting etc. These tables are for prototype and pre-production modules only.
>
>
A list of production PDMDBs delivered to CERN can be found here.
 
Added:
>
>
There are also a number of prototype boards in circulation. The lists of these are tabulated below. The Excel files are convenient for sorting etc. These tables are for prototype and pre-production modules only.

Prototypes
 
PDMDB TCM DTM
WWW WWW WWW
.xlsx .xlsx .xlsx
\ No newline at end of file

Revision 312019-02-25 - StephenWotton

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META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 39 to 39
  In the muDAQ environment, the above settings are used identically on all DTMs.
Added:
>
>
ALERT! There seems to be some numbering confusion for the uplinks used in widebus mode. In 320Mbs mode, the manual names the uplinks as dIO1,5,9,13 for groups 5 and 6 (the other groups use dOut0,4...). However, dIO1 is enabled using bit 0 in the enable and train configuration registers but bit 1 is used for the terminations register.
 

TCM

Minimal fuse settings 1.

Revision 302019-02-21 - StephenWotton

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META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 33 to 33
  The DTM GBTX settings are based on the xPLL-bypassed configuration.
Changed:
<
<
At least one DTM appears to require the e-group phase-aligner PLL to be reset after configuration. Since this could be due to process variation it may also be the case for others. Therefore it is advisable to do a phase-aligner PLL reset after configuration for all of the DTMs. There is one reset per e-link group.
>
>
One prototype DTM (#19) appears to require the e-group phase-aligner PLL to be reset after configuration. This is likely to be because GBTX0 has been e-fused. A reset sequence similar to that recommended for e-fused TCMs is therefore advisable for this DTM. It is not recommended to do this for production DTMs since the GBTXs are not efused and the correct sequence of resets is issued by the startup FSM.
 
Changed:
<
<
The phase of the data transmission e-links must also be adjusted. Empirically, a value of 5 in the eport.pa.*.0.phase and eport.pa.*.4.phase gives good results for all e-links with no bitflips seen. More fine-grained tuning could give greater margins but does not seem to be necessary in practice.
>
>
The phase of the data transmission e-links must also be adjusted. Empirically, a value of 5 in the eport.pa.*.0.phase and eport.pa.*.4.phase gives good results for all e-links with no bitflips seen. The strategy may need to be reviewed in the light of the production testing if significant variations are seen.
  In the muDAQ environment, the above settings are used identically on all DTMs.
Line: 74 to 74
 
eport.pa.coarse-lock 0x1 3.

Notes:

Changed:
<
<
  1. For e-fused GBTXs, after power up, the remaining registers must be loaded and the e-port phase aligners must then be manually reset.
>
>
  1. For e-fused GBTXs, after power up, the remaining registers must be loaded and some GBTX functions must be reset following the recommendation below.
 
  1. This value is not critical. The CDR appears to lock even for extreme values of this setting.
  2. It is probably convenient also that the EC (SCA) e-port also comes alive at power up.
Line: 124 to 124
  The following steps are recommended to complete the configuration of e-fused master GBTXs:
Changed:
<
<
  1. Power up. The master link should come up automatically, but not necessarily the SCA.
>
>
  1. Power up. The master link and EC (SCA) e-port should come up automatically.
  2. At this point the SCA chip should be accessible and could be set up and used if needed (e.g. for temperature monitoring).
 
  1. Write GBTX registers to disable the watchdog and timeout features (without touching other registers).
  2. Load the full configuration file (which must have the watchdog and timeout registers still disabled and must not modify the e-fused registers.)
Changed:
<
<
  1. Write GBTX registers to assert and then deassert the e-port phase aligner resets. At this point the SCA chip should be accessible (but not yet configured).
>
>
  1. Write GBTX registers to assert and then deassert the e-port phase aligner resets.
  2. Write GBTX registers to assert and deassert the phase shifter PLL and DLLs respecting the ordering and the required locking times.
 
  1. Write GBTX registers to re-enable the timeout and watchdog.
Changed:
<
<
  1. Continue with system configuration.
>
>
  1. Continue with system configuration including SCA set-up if not already done.
 
Changed:
<
<
The interplay between the watchdog and timeout logic may cause the soft configuration to be lost (if the master link loses lock for example) and under these circumstances will need to be reconfigured from step 2. It may not happen in practice but it is a possibility. It can be detected by reading a GBTX register that contains zero but should be non-zero.
>
>
The interplay between the watchdog and timeout logic may cause the soft configuration to be lost (if the master link loses lock for example) and under these circumstances will need to be reconfigured from step 3. It may not happen in practice but it is a possibility. It can be detected by reading a GBTX register that contains zero but should be non-zero.
  The above does not apply to the DTMs. These GBTXs can simply be configured as we do now.

Revision 292019-02-17 - StephenWotton

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META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 68 to 68
 
serialiser.current 0x8
serialiser.resistor 0x2
tx.select-positive-edge 0x1
Added:
>
>
eport.pa.ec.config 0xd 3.
eport.pa.ec.enable 0x1 3.
eport.pa.ec.termination 0x1 3.
eport.pa.coarse-lock 0x1 3.
  Notes:
  1. For e-fused GBTXs, after power up, the remaining registers must be loaded and the e-port phase aligners must then be manually reset.
  2. This value is not critical. The CDR appears to lock even for extreme values of this setting.
Added:
>
>
  1. It is probably convenient also that the EC (SCA) e-port also comes alive at power up.
  The GBTX register descriptions are summarised here for reference.
Line: 94 to 99
 [048,030] 15 [050,032] 07 [052,034] 38
Added:
>
>
[231,0e7] DD [232,0e8] 0D [233,0e9] 70
 [244,0f4] 38
Added:
>
>
[248,0f8] 07 [273,111] 20
 [281,119] 15 [313,139] 5D [314,13a] 5D
Line: 102 to 112
 [316,13c] AA [317,13d] 0A [318,13e] 07
Deleted:
<
<
[365,16d] AA
 

With the above settings, the link appears to automatically re-establish if the master link is temporarily down.

Revision 282019-02-14 - StephenWotton

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META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 113 to 113
  Production TCMs are factory-configured to default to the fibre configuration interface. When used in the standard way, the I2C interface is inactive.
Added:
>
>
The following steps are recommended to complete the configuration of e-fused master GBTXs:

  1. Power up. The master link should come up automatically, but not necessarily the SCA.
  2. Write GBTX registers to disable the watchdog and timeout features (without touching other registers).
  3. Load the full configuration file (which must have the watchdog and timeout registers still disabled and must not modify the e-fused registers.)
  4. Write GBTX registers to assert and then deassert the e-port phase aligner resets. At this point the SCA chip should be accessible (but not yet configured).
  5. Write GBTX registers to re-enable the timeout and watchdog.
  6. Continue with system configuration.

The interplay between the watchdog and timeout logic may cause the soft configuration to be lost (if the master link loses lock for example) and under these circumstances will need to be reconfigured from step 2. It may not happen in practice but it is a possibility. It can be detected by reading a GBTX register that contains zero but should be non-zero.

The above does not apply to the DTMs. These GBTXs can simply be configured as we do now.

 

Testing

See RichPdmdbProductionTesting.

Revision 272019-02-13 - StephenWotton

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META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 41 to 41
 

TCM

Changed:
<
<
Minimal fuse settings
Name Value
watchdog.startup-timeout-enable 0x1
watchdog.enable 0x1
xpll.frequency-trim 0x5d
xpll.control-override 0x1
xpll.gm-select 0xa
cm.refclk.select 0x1
efuse.update.enable 0x1
deserialiser.resistor 0xd
rx.frequency-detector 0x2
rx.phase-detector 0x4
rx.valid-headers 0xf
rx.max-invalid-headers 0x4
rx.min-valid-headers 0x8
rx.select-i1 0x2
rx.switch.0 0x1
rx.switch.1 0x1
rx.switch.2 0x1
tx.switch.0 0x1
tx.switch.1 0x1
tx.switch.2 0x1
serialiser.lock-time 0x6
serialiser.unlock-time 0x3
serialiser.current 0x8
serialiser.resistor 0x2
tx.select-positive-edge 0x1
>
>
Minimal fuse settings 1.
Name Value Note
watchdog.startup-timeout-enable 0x1
watchdog.enable 0x1
xpll.frequency-trim 0x5d 2.
xpll.control-override 0x1
xpll.gm-select 0xa
cm.refclk.select 0x1
efuse.update.enable 0x1
deserialiser.resistor 0xd
rx.frequency-detector 0x2
rx.phase-detector 0x4
rx.valid-headers 0xf
rx.max-invalid-headers 0x4
rx.min-valid-headers 0x8
rx.select-i1 0x2
rx.switch.0 0x1
rx.switch.1 0x1
rx.switch.2 0x1
tx.switch.0 0x1
tx.switch.1 0x1
tx.switch.2 0x1
serialiser.lock-time 0x6
serialiser.unlock-time 0x3
serialiser.current 0x8
serialiser.resistor 0x2
tx.select-positive-edge 0x1

Notes:

  1. For e-fused GBTXs, after power up, the remaining registers must be loaded and the e-port phase aligners must then be manually reset.
  2. This value is not critical. The CDR appears to lock even for extreme values of this setting.
  The GBTX register descriptions are summarised here for reference.

Revision 262019-02-07 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 74 to 74
 Here is the resulting list of non-zero bytes to be e-fused:
Changed:
<
<
[029] 15 [030] 15 [031] 15 [032] 66 [035] 42 [046] 15 [047] 15 [048] 15 [050] 07 [052] 38 [281] 15 [313] 5D [314] 5D [315] 5D [316] AA [317] 0A [318] 07 [366] 07
>
>
[027,01b] 28 [029,01d] 15 [030,01e] 15 [031,01f] 15 [032,020] 66 [034,022] 0D [035,023] 42 [037,025] 0F [038,026] 04 [039,027] 08 [041,029] 20 [046,02e] 15 [047,02f] 15 [048,030] 15 [050,032] 07 [052,034] 38 [244,0f4] 38 [281,119] 15 [313,139] 5D [314,13a] 5D [315,13b] 5D [316,13c] AA [317,13d] 0A [318,13e] 07 [365,16d] AA
 

With the above settings, the link appears to automatically re-establish if the master link is temporarily down.

Revision 252019-02-07 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 65 to 65
 
tx.switch.2 0x1
serialiser.lock-time 0x6
serialiser.unlock-time 0x3
Added:
>
>
serialiser.current 0x8
serialiser.resistor 0x2
tx.select-positive-edge 0x1
  The GBTX register descriptions are summarised here for reference.

Revision 242019-02-07 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 50 to 50
 
xpll.gm-select 0xa
cm.refclk.select 0x1
efuse.update.enable 0x1
Added:
>
>
deserialiser.resistor 0xd
 
rx.frequency-detector 0x2
rx.phase-detector 0x4
rx.valid-headers 0xf
rx.max-invalid-headers 0x4
rx.min-valid-headers 0x8
Added:
>
>
rx.select-i1 0x2
 
rx.switch.0 0x1
rx.switch.1 0x1
rx.switch.2 0x1

Revision 232019-02-07 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 52 to 52
 
efuse.update.enable 0x1
rx.frequency-detector 0x2
rx.phase-detector 0x4
Added:
>
>
rx.valid-headers 0xf
rx.max-invalid-headers 0x4
rx.min-valid-headers 0x8
 
rx.switch.0 0x1
rx.switch.1 0x1
rx.switch.2 0x1

Revision 222018-11-30 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 100 to 100
 

Inventory

Changed:
<
<
The web pages are generated from XML data and are more authoritative. The Excel files are convenient for sorting etc.
>
>
The web pages are generated from XML data and are more authoritative. The Excel files are convenient for sorting etc. These tables are for prototype and pre-production modules only.
 
PDMDB TCM DTM
WWW WWW WWW

Revision 212018-10-15 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Added:
>
>
The information provided here complements the information found in

Documents
PDMDB motherboard
PDMDB TCM/DTM plug-ins
 The RICH PDMDB provides the configuration and data interface between the elementary cells and the LHCb readout system (or miniDAQ or RichMuDaq). The hardware is based on 3 Xilinx Kintex7 FPGAs that capture the FE data from the digital CLARO outputs and forward them to the readout sytstem via 3 DTM (Data Transmission Module) plug-ins that each implement two GBT links. The PDMDB is controlled through a TCM (Trigger and Control Module) plug-in that implements the LHCb configuration and fast control interface over one bi-directional GBT link.

ALERT!The sketch below illustrates the R-type PDMDB. The H-type PDMDB has two DTMs and two FPGAs (FPGA.1 and DTM.1 are removed and the MAPMT signals redistributed).

Revision 202018-10-14 - StephenWotton

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META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 25 to 25
 

DTM

Added:
>
>
The DTM GBTX settings are based on the xPLL-bypassed configuration.
 At least one DTM appears to require the e-group phase-aligner PLL to be reset after configuration. Since this could be due to process variation it may also be the case for others. Therefore it is advisable to do a phase-aligner PLL reset after configuration for all of the DTMs. There is one reset per e-link group.

The phase of the data transmission e-links must also be adjusted. Empirically, a value of 5 in the eport.pa.*.0.phase and eport.pa.*.4.phase gives good results for all e-links with no bitflips seen. More fine-grained tuning could give greater margins but does not seem to be necessary in practice.

In the muDAQ environment, the above settings are used identically on all DTMs.

Changed:
<
<

TCM minimal e-fuse settings

>
>

TCM

 
Added:
>
>
Minimal fuse settings
 
Name Value
watchdog.startup-timeout-enable 0x1
watchdog.enable 0x1
Line: 52 to 55
 
serialiser.lock-time 0x6
serialiser.unlock-time 0x3
Changed:
<
<
The GBTX registers are summarised here for reference.

With the above settings, the link appears to automatically re-establish if the master link is temporarily down.

IDEA! Only registers that differ from 0 are listed. The set is based on the xPLL-bypassed configuration.

ALERT! Once efuse.update.enable is programmed, configuration will no longer pause at pauseForConfig and all other registers will contain 0 until programmed through the SC or or I2C interface.

>
>
The GBTX register descriptions are summarised here for reference.
  Here is the resulting list of non-zero bytes to be e-fused:
Line: 83 to 80
 [366] 07
Added:
>
>
With the above settings, the link appears to automatically re-establish if the master link is temporarily down.

IDEA! Only registers that differ from 0 are listed. The set is based on the xPLL-bypassed (VCXO) configuration.

ALERT! Once efuse.update.enable is programmed, configuration will no longer pause at pauseForConfig and all other registers will contain 0 until programmed through the fibre or or I2C interface.

Production TCMs are factory-configured to default to the fibre configuration interface. When used in the standard way, the I2C interface is inactive.

 

Testing

See RichPdmdbProductionTesting.

Revision 192018-10-05 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 23 to 23
  The latest PDMDB hardware provides both 40MHz and 160MHz synchronous clocks to the FPGA. This greatly simplifies the link synchronisation of the data transmission links. For the synchronisation with GBTX.0, the FPGA serialiser 40MHz clock needs only to be delayed by a fixed amount relative to the input 40MHz clock and the serialisers reset synchronously. This can be done on power-up reset of the FPGA using fixed internal shift-register delays so no external tuning is required. However, it has not yet been demonstrated that the same delay can be used for all FPGAs on all boards. For synchronisation with GBTX.1, exactly the same settings can be used but the correct phase of its 40MHz input reference clock must be found. Empirically, setting ps.0.coarse-delay register to 15 appears to give good results.
Added:
>
>

DTM

At least one DTM appears to require the e-group phase-aligner PLL to be reset after configuration. Since this could be due to process variation it may also be the case for others. Therefore it is advisable to do a phase-aligner PLL reset after configuration for all of the DTMs. There is one reset per e-link group.

 The phase of the data transmission e-links must also be adjusted. Empirically, a value of 5 in the eport.pa.*.0.phase and eport.pa.*.4.phase gives good results for all e-links with no bitflips seen. More fine-grained tuning could give greater margins but does not seem to be necessary in practice.

In the muDAQ environment, the above settings are used identically on all DTMs.

Revision 182018-10-03 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 85 to 85
 

Inventory

Deleted:
<
<
PDMDB TCM DTM
 \ No newline at end of file
Added:
>
>
The web pages are generated from XML data and are more authoritative. The Excel files are convenient for sorting etc.

PDMDB TCM DTM
WWW WWW WWW
.xlsx .xlsx .xlsx

Revision 172018-10-03 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 82 to 82
 

Testing

See RichPdmdbProductionTesting. \ No newline at end of file

Added:
>
>

Inventory

PDMDB TCM DTM
 \ No newline at end of file

Revision 162018-09-30 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 56 to 56
  ALERT! Once efuse.update.enable is programmed, configuration will no longer pause at pauseForConfig and all other registers will contain 0 until programmed through the SC or or I2C interface.
Added:
>
>
Here is the resulting list of non-zero bytes to be e-fused:

[029] 15
[030] 15
[031] 15
[032] 66
[035] 42
[046] 15
[047] 15
[048] 15
[050] 07
[052] 38
[281] 15
[313] 5D
[314] 5D
[315] 5D
[316] AA
[317] 0A
[318] 07
[366] 07
 

Testing

See RichPdmdbProductionTesting.

Revision 152018-09-30 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 30 to 30
 

TCM minimal e-fuse settings

Name Value
Added:
>
>
watchdog.startup-timeout-enable 0x1
watchdog.enable 0x1
 
xpll.frequency-trim 0x5d
xpll.control-override 0x1
xpll.gm-select 0xa
cm.refclk.select 0x1
efuse.update.enable 0x1
Added:
>
>
rx.frequency-detector 0x2
rx.phase-detector 0x4
rx.switch.0 0x1
rx.switch.1 0x1
rx.switch.2 0x1
tx.switch.0 0x1
tx.switch.1 0x1
tx.switch.2 0x1
serialiser.lock-time 0x6
serialiser.unlock-time 0x3
 
Changed:
<
<
IDEA! Only registers that differ from 0 are listed.
>
>
The GBTX registers are summarised here for reference.

With the above settings, the link appears to automatically re-establish if the master link is temporarily down.

IDEA! Only registers that differ from 0 are listed. The set is based on the xPLL-bypassed configuration.

  ALERT! Once efuse.update.enable is programmed, configuration will no longer pause at pauseForConfig and all other registers will contain 0 until programmed through the SC or or I2C interface.

Revision 142018-09-26 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 27 to 27
  In the muDAQ environment, the above settings are used identically on all DTMs.
Added:
>
>

TCM minimal e-fuse settings

Name Value
xpll.frequency-trim 0x5d
xpll.control-override 0x1
xpll.gm-select 0xa
cm.refclk.select 0x1
efuse.update.enable 0x1

IDEA! Only registers that differ from 0 are listed.

ALERT! Once efuse.update.enable is programmed, configuration will no longer pause at pauseForConfig and all other registers will contain 0 until programmed through the SC or or I2C interface.

 

Testing

See RichPdmdbProductionTesting.

Revision 132018-08-27 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 19 to 19
 
R1 (R-type production) View View View
H1 (H-type production) View View View
Added:
>
>

Synchronisation and timing

The latest PDMDB hardware provides both 40MHz and 160MHz synchronous clocks to the FPGA. This greatly simplifies the link synchronisation of the data transmission links. For the synchronisation with GBTX.0, the FPGA serialiser 40MHz clock needs only to be delayed by a fixed amount relative to the input 40MHz clock and the serialisers reset synchronously. This can be done on power-up reset of the FPGA using fixed internal shift-register delays so no external tuning is required. However, it has not yet been demonstrated that the same delay can be used for all FPGAs on all boards. For synchronisation with GBTX.1, exactly the same settings can be used but the correct phase of its 40MHz input reference clock must be found. Empirically, setting ps.0.coarse-delay register to 15 appears to give good results.

The phase of the data transmission e-links must also be adjusted. Empirically, a value of 5 in the eport.pa.*.0.phase and eport.pa.*.4.phase gives good results for all e-links with no bitflips seen. More fine-grained tuning could give greater margins but does not seem to be necessary in practice.

In the muDAQ environment, the above settings are used identically on all DTMs.

 

Testing

See RichPdmdbProductionTesting.

Revision 122018-05-03 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

The RICH PDMDB provides the configuration and data interface between the elementary cells and the LHCb readout system (or miniDAQ or RichMuDaq). The hardware is based on 3 Xilinx Kintex7 FPGAs that capture the FE data from the digital CLARO outputs and forward them to the readout sytstem via 3 DTM (Data Transmission Module) plug-ins that each implement two GBT links. The PDMDB is controlled through a TCM (Trigger and Control Module) plug-in that implements the LHCb configuration and fast control interface over one bi-directional GBT link.

Added:
>
>
ALERT!The sketch below illustrates the R-type PDMDB. The H-type PDMDB has two DTMs and two FPGAs (FPGA.1 and DTM.1 are removed and the MAPMT signals redistributed).

ALERT!The sketch does not correctly reflect the actual order of the FPGAs on the JTAG chain. The order is TAP→FPGA.2→FPGA.1→FPGA.0→TAP. The order is not the same on prototype boards.

 muDAQ

Mappings

Line: 17 to 21
 

Testing

Changed:
<
<
Three testing phases:

  1. Viisual inspection and basic powering test using Philip's board connected to testing edge connector.
  2. Basic set-up of board.
  3. Statistical tests.

ALERT!Testing hardware/software/firmware needs to compatible with both R-type and H-type modules.

Phase 1

Cambridge. Before mounting of TCMs and DTMs. Use power testing board with microcontroller.

  • Check that excessive current is not drawn.
  • Check all voltage levels within acceptable limits.
  • Check FPGA JTAG?
  • Mount TCM's DTMs
  • Recheck voltages. Check currents.

Phase 2

Oxford/Romania/(Cambridge).

The aim of this is to quickly establish that the basic functionality is good.

  • Couple to Rui's board
  • Check that excessive current is not drawn.
  • Basic board set-up
    • Establish master link
    • Check lock
    • Record eye diagram
    • Establish and check link with SCA
    • I2C - Configure and verify GBTX configuration in DTM.
    • JTAG read/check FPGA IDCODE
  • FPGA configuration
    • Load bitstream. Readback status register.
    • FPGA testing firmware will need to implement I2C slave and status registers.
    • The FPGAs are attached to the same SCA I2C bus as the GBTXs on the corresponding DTM.
    • Readback of bitstream is not needed since succesful FPGA startup requires successful CRC check.
    • Check also internal temperature sensor and VCCint and VCCaux sensors.
  • DTM
    • Write and verify configuration with I2C
    • Check GBTX status (lock, power-up FSM)
    • Put GBTX into AABB mode and check pattern in muDaq
    • Record eye diagrams
  • ADC/DAC
    • Loopback DAC to ADC inputs via Rui's board and check with muDaq or
    • Use combination of Rui's board and muDaq to check.
    • Set a voltage and check that the value is reasonable.
    • NB: take care when configuring SCA ADC current source.
  • EC GPIOs
    • Either loop them back through Rui's board and perform tests via muDaq or
    • use combination of muDaq and Rui's board to read and write.
  • SPI
    • This requires Rui's board to act as a simple SPI slave.
    • Check each SPI slave select is correctly asserted.
    • Check the function of write enable and feb enables (can be done during GPIO checks).
    • SCA-SPI master sends pattern to MOSI, slave loops back to MISO. Check the pattern agrees.
  • EC MAPMT IOs
    • Shift PRBS through chain of looped back IOs
    • Implement e.g. LFSR in FPGA firmware and counters to count bit errors.
    • Use I2C slave implementation monitor through master link.
  • Down links
    • Use muDaq to write pattern on downlink
    • Implement I2C register in FPGA for readback verification of written pattern.
  • Other
    • Check function of FPGA power enable GPIO.
    • Check PDMDB power sense ADC values are within acceptable limits.

Phase 3

Oxford/Romania/(Cambridge).

In this phase, the reliability is tested by repeated cycles of as many features as possible. It is possible that BER of the data links might have to be deferred to CERN because the muDAQ may not have the necessary capability.

  • Repeat GBTX configuration write/verify cycle.
  • Repeat FPGA program/verify cycle
  • Repeat SPI write verify cycle.
  • Repeat MAPMT IO tests
>
>
See RichPdmdbProductionTesting.

Revision 112018-05-02 - StephenWotton

Line: 1 to 1
 
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PDMDB

Line: 15 to 15
 
R1 (R-type production) View View View
H1 (H-type production) View View View
Changed:
<
<

DTM

>
>

Testing

 
Changed:
<
<

Clocks

>
>
Three testing phases:
 
Changed:
<
<
Several clocking schemes are possible in principle:

160MHz DTM reference clock.

This has the advantage that a PLL may not be needed since a simple clock divider can be used to generate the 40MHz clock. However, it comes with the disadvantage that the phase ambiguity of the VTRX 40MHz clock and the DTM 40 MHz clock must be resolved.

40MHz DTM reference clock.

A PLL is needed to generate a 160MHz clock but the 40MHz phase ambiguity is removed.

Phase aligned 160MHz and 40MHz reference clocks

This is not currently supported by the hardware. A future version could implement a second reference clock input to the DTM. Both 160MHz and 40MHz reference clocks would be driven from the TCM module and have a constant but programmable alignment.

e-link fine timing

The up e-links operate in 320Mb/s (160MHz DDR) mode. The GBTX receivers must be phase-aligned to the data for reliable transmission. It is quite likely, though not yet established, that a common setting will work on all links on all boards.

It is not clear whether the GBTX manual correctly documents which registers correspond to which channels. However, as it appears that the same value can be used everywhere, it is OK to write the value into all the e-link phase alignment registers even for the inactive e-links.

Note that this adjustment does not resolve the 40MHz clock ambiguity. It is used only to position the sampling clock in the centre of the stable data region.

40MHz clock ambiguity

Since the DTM e-links are operating as 8:1 serialisers, there is in principle an 8-fold ambiguity in the phase relative to the receiving 40MHz clock. This is reduced to a 4-fold ambiguity because the DTM 40MHz clock is aligned to the rising edge of the 160MHz reference clock. There is a therefore a 1-in-4 chance of hitting on the correct alignment every time the PDMDB clock divider is reset.

Since there are spare bits in the GBTX frame, the current phase alignment can be monitored by transmitting a fixed, 8-bit wide pattern (e.g. 00000001) and observing where the 1 appears in the byte at the receiver. This information can be used (with a suitable synchronous reset mechanism in the PDMDB) to allow the correct adjustment of the 40MHz clock phase at the transmitter. Another possibility is to exploit the fact that there is no phase ambiguity for the TFC commands received by the PDMDB FPGAs. The PDMDB can exploit this by aligning the 40MHz clock to the TFC command. This results in a deterministic phase relationship between the TCM and DTM 40 MHz clocks.

e-link clocking

A method that avoids the use of a PLL while still allowing the coarse alignment of the e-links and to account for the 40MHz clock ambiguity uses a combination of BUFRs and BUFIOs. The BUFR has a built-in clock divider that allows the 40 MHz clock to be derived from the 160 MHz reference clock. Certain placement rules must be respected since a BUFR or BUFIO can only drive clock loads within its own clock region (IO bank). The e-links are spread across two clock regions therefore two BUFR/BUFIO combinations are required. These must be driven by a single multi-region clock buffer (BUFMR) which is itself driven by the 160 MHz reference clock pin.

The recommended way to synchronously start up this clock tree is to use the CE input of the BUFMRCE to disable the clock, then reset the BUFR (and the OSERDES that it drives). The BUFMR can then be renabled. Delaying the re-enabling allows the phase of the local 40 MHz clock to be controlled. This can be achieved using a shift register (e.g. SRL16E) clocked by the 160MHz reference clock. One of the TFC commands on the downlink is selected to start this clock reset sequence. Because the command has a known phase relative to the TFC source clock this results in the local 40MHz clock having a deterministic phase relative to the source clock with the phase adjusted by means of the shift register. The TFC command must be taken directly from the e-link without being re-aligned to a local clock for this method to work because otherwise the phase information that it carries would be lost.

The detailed implementation is a little bit fiddly due to the sharing of the e-links across two clock regions and there are a few places where the clock phases have to be carefully selected. There is also an additional phase adjustment needed to align the data for DTMx.GBT1 since its 40MHz clock is 180 deg out of phase with DTMx.GBT0. However, having done all this, the two DTMs appear to reliably adjust themselves to the correct phase in response to the TFC command. The command should be issued whenever the DTM or FPGA are reset. Since two TFC commands are multplexed onto a single e-link (with different but known phase wrt to the 40MHz clock), a simple protocol is needed to ensure that only the selected TFC command may initiate the re-alignment.

Note that, with this implementation, it appears that the default settings (0) of the e-link phase in the GBTX are satisfactory.

>
>
  1. Viisual inspection and basic powering test using Philip's board connected to testing edge connector.
  2. Basic set-up of board.
  3. Statistical tests.

ALERT!Testing hardware/software/firmware needs to compatible with both R-type and H-type modules.

Phase 1

Cambridge. Before mounting of TCMs and DTMs. Use power testing board with microcontroller.

  • Check that excessive current is not drawn.
  • Check all voltage levels within acceptable limits.
  • Check FPGA JTAG?
  • Mount TCM's DTMs
  • Recheck voltages. Check currents.

Phase 2

Oxford/Romania/(Cambridge).

The aim of this is to quickly establish that the basic functionality is good.

  • Couple to Rui's board
  • Check that excessive current is not drawn.
  • Basic board set-up
    • Establish master link
    • Check lock
    • Record eye diagram
    • Establish and check link with SCA
    • I2C - Configure and verify GBTX configuration in DTM.
    • JTAG read/check FPGA IDCODE
  • FPGA configuration
    • Load bitstream. Readback status register.
    • FPGA testing firmware will need to implement I2C slave and status registers.
    • The FPGAs are attached to the same SCA I2C bus as the GBTXs on the corresponding DTM.
    • Readback of bitstream is not needed since succesful FPGA startup requires successful CRC check.
    • Check also internal temperature sensor and VCCint and VCCaux sensors.
  • DTM
    • Write and verify configuration with I2C
    • Check GBTX status (lock, power-up FSM)
    • Put GBTX into AABB mode and check pattern in muDaq
    • Record eye diagrams
  • ADC/DAC
    • Loopback DAC to ADC inputs via Rui's board and check with muDaq or
    • Use combination of Rui's board and muDaq to check.
    • Set a voltage and check that the value is reasonable.
    • NB: take care when configuring SCA ADC current source.
  • EC GPIOs
    • Either loop them back through Rui's board and perform tests via muDaq or
    • use combination of muDaq and Rui's board to read and write.
  • SPI
    • This requires Rui's board to act as a simple SPI slave.
    • Check each SPI slave select is correctly asserted.
    • Check the function of write enable and feb enables (can be done during GPIO checks).
    • SCA-SPI master sends pattern to MOSI, slave loops back to MISO. Check the pattern agrees.
  • EC MAPMT IOs
    • Shift PRBS through chain of looped back IOs
    • Implement e.g. LFSR in FPGA firmware and counters to count bit errors.
    • Use I2C slave implementation monitor through master link.
  • Down links
    • Use muDaq to write pattern on downlink
    • Implement I2C register in FPGA for readback verification of written pattern.
  • Other
    • Check function of FPGA power enable GPIO.
    • Check PDMDB power sense ADC values are within acceptable limits.

Phase 3

Oxford/Romania/(Cambridge).

In this phase, the reliability is tested by repeated cycles of as many features as possible. It is possible that BER of the data links might have to be deferred to CERN because the muDAQ may not have the necessary capability.

  • Repeat GBTX configuration write/verify cycle.
  • Repeat FPGA program/verify cycle
  • Repeat SPI write verify cycle.
  • Repeat MAPMT IO tests

Revision 102018-04-27 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 6 to 6
  muDAQ
Changed:
<
<

V1 (prototype) mappings

>
>

Mappings

  Note that the EC index is the PDMDB PCB ordering. The mapping to the physical ECs must take account of the relative rotation of the two PDMDBs on the PDM.
Changed:
<
<

R1 (R-type production) mappings

Note that the EC index is the PDMDB PCB ordering. The mapping to the physical ECs must take account of the relative rotation of the two PDMDBs on the PDM.

>
>
Board type PDMDB EC DTM
V1 (prototype) View View View
R1 (R-type production) View View View
H1 (H-type production) View View View
 

DTM

Revision 92018-04-14 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 17 to 17
  Note that the EC index is the PDMDB PCB ordering. The mapping to the physical ECs must take account of the relative rotation of the two PDMDBs on the PDM.
Added:
>
>
 

Revision 82018-03-10 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 6 to 6
  muDAQ
Changed:
<
<

V1 mappings

>
>

V1 (prototype) mappings

  Note that the EC index is the PDMDB PCB ordering. The mapping to the physical ECs must take account of the relative rotation of the two PDMDBs on the PDM.

Added:
>
>

R1 (R-type production) mappings

Note that the EC index is the PDMDB PCB ordering. The mapping to the physical ECs must take account of the relative rotation of the two PDMDBs on the PDM.

 

DTM

Clocks

Revision 72018-02-20 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

The RICH PDMDB provides the configuration and data interface between the elementary cells and the LHCb readout system (or miniDAQ or RichMuDaq). The hardware is based on 3 Xilinx Kintex7 FPGAs that capture the FE data from the digital CLARO outputs and forward them to the readout sytstem via 3 DTM (Data Transmission Module) plug-ins that each implement two GBT links. The PDMDB is controlled through a TCM (Trigger and Control Module) plug-in that implements the LHCb configuration and fast control interface over one bi-directional GBT link.

Added:
>
>
muDAQ
 

V1 mappings

Note that the EC index is the PDMDB PCB ordering. The mapping to the physical ECs must take account of the relative rotation of the two PDMDBs on the PDM.

Added:
>
>
 

DTM

Revision 62018-02-20 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 8 to 8
  Note that the EC index is the PDMDB PCB ordering. The mapping to the physical ECs must take account of the relative rotation of the two PDMDBs on the PDM.
Changed:
<
<
>
>
 

DTM

Revision 52018-02-20 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

The RICH PDMDB provides the configuration and data interface between the elementary cells and the LHCb readout system (or miniDAQ or RichMuDaq). The hardware is based on 3 Xilinx Kintex7 FPGAs that capture the FE data from the digital CLARO outputs and forward them to the readout sytstem via 3 DTM (Data Transmission Module) plug-ins that each implement two GBT links. The PDMDB is controlled through a TCM (Trigger and Control Module) plug-in that implements the LHCb configuration and fast control interface over one bi-directional GBT link.

Added:
>
>

V1 mappings

Note that the EC index is the PDMDB PCB ordering. The mapping to the physical ECs must take account of the relative rotation of the two PDMDBs on the PDM.

 

DTM

Clocks

Revision 42017-04-07 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 8 to 8
 

Clocks

Added:
>
>
Several clocking schemes are possible in principle:
 

160MHz DTM reference clock.

This has the advantage that a PLL may not be needed since a simple clock divider can be used to generate the 40MHz clock. However, it comes with the disadvantage that the phase ambiguity of the VTRX 40MHz clock and the DTM 40 MHz clock must be resolved.

Line: 33 to 35
 Since the DTM e-links are operating as 8:1 serialisers, there is in principle an 8-fold ambiguity in the phase relative to the receiving 40MHz clock. This is reduced to a 4-fold ambiguity because the DTM 40MHz clock is aligned to the rising edge of the 160MHz reference clock. There is a therefore a 1-in-4 chance of hitting on the correct alignment every time the PDMDB clock divider is reset.

Since there are spare bits in the GBTX frame, the current phase alignment can be monitored by transmitting a fixed, 8-bit wide pattern (e.g. 00000001) and observing where the 1 appears in the byte at the receiver. This information can be used (with a suitable synchronous reset mechanism in the PDMDB) to allow the correct adjustment of the 40MHz clock phase at the transmitter. Another possibility is to exploit the fact that there is no phase ambiguity for the TFC commands received by the PDMDB FPGAs. The PDMDB can exploit this by aligning the 40MHz clock to the TFC command. This results in a deterministic phase relationship between the TCM and DTM 40 MHz clocks.

Added:
>
>

e-link clocking

A method that avoids the use of a PLL while still allowing the coarse alignment of the e-links and to account for the 40MHz clock ambiguity uses a combination of BUFRs and BUFIOs. The BUFR has a built-in clock divider that allows the 40 MHz clock to be derived from the 160 MHz reference clock. Certain placement rules must be respected since a BUFR or BUFIO can only drive clock loads within its own clock region (IO bank). The e-links are spread across two clock regions therefore two BUFR/BUFIO combinations are required. These must be driven by a single multi-region clock buffer (BUFMR) which is itself driven by the 160 MHz reference clock pin.

The recommended way to synchronously start up this clock tree is to use the CE input of the BUFMRCE to disable the clock, then reset the BUFR (and the OSERDES that it drives). The BUFMR can then be renabled. Delaying the re-enabling allows the phase of the local 40 MHz clock to be controlled. This can be achieved using a shift register (e.g. SRL16E) clocked by the 160MHz reference clock. One of the TFC commands on the downlink is selected to start this clock reset sequence. Because the command has a known phase relative to the TFC source clock this results in the local 40MHz clock having a deterministic phase relative to the source clock with the phase adjusted by means of the shift register. The TFC command must be taken directly from the e-link without being re-aligned to a local clock for this method to work because otherwise the phase information that it carries would be lost.

The detailed implementation is a little bit fiddly due to the sharing of the e-links across two clock regions and there are a few places where the clock phases have to be carefully selected. There is also an additional phase adjustment needed to align the data for DTMx.GBT1 since its 40MHz clock is 180 deg out of phase with DTMx.GBT0. However, having done all this, the two DTMs appear to reliably adjust themselves to the correct phase in response to the TFC command. The command should be issued whenever the DTM or FPGA are reset. Since two TFC commands are multplexed onto a single e-link (with different but known phase wrt to the 40MHz clock), a simple protocol is needed to ensure that only the selected TFC command may initiate the re-alignment.

Note that, with this implementation, it appears that the default settings (0) of the e-link phase in the GBTX are satisfactory.

Revision 32017-04-06 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

Line: 22 to 22
 

e-link fine timing

Changed:
<
<
The up e-links operate in 320Mb/s (160MHz DDR) mode. The GBTX receivers must be phase-aligned to the data for reliable transmission. The default settings do not appear to be optimal for the PDMDB. A phase shift of about 90deg seems to give good results. All used e-links should therefore have the value 3 written in the per-link phase alignment register. It is quite likely, though not yet established, that a common setting will work on all links on all boards.
>
>
The up e-links operate in 320Mb/s (160MHz DDR) mode. The GBTX receivers must be phase-aligned to the data for reliable transmission. It is quite likely, though not yet established, that a common setting will work on all links on all boards.
  It is not clear whether the GBTX manual correctly documents which registers correspond to which channels. However, as it appears that the same value can be used everywhere, it is OK to write the value into all the e-link phase alignment registers even for the inactive e-links.
Changed:
<
<
Note that this adjustment does not resolve the 40MHz clock ambiguity. It is used only to centre the sampling clock in the centre of the stable data region.
>
>
Note that this adjustment does not resolve the 40MHz clock ambiguity. It is used only to position the sampling clock in the centre of the stable data region.
 

40MHz clock ambiguity

Revision 22017-04-06 - StephenWotton

Line: 1 to 1
 
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

The RICH PDMDB provides the configuration and data interface between the elementary cells and the LHCb readout system (or miniDAQ or RichMuDaq). The hardware is based on 3 Xilinx Kintex7 FPGAs that capture the FE data from the digital CLARO outputs and forward them to the readout sytstem via 3 DTM (Data Transmission Module) plug-ins that each implement two GBT links. The PDMDB is controlled through a TCM (Trigger and Control Module) plug-in that implements the LHCb configuration and fast control interface over one bi-directional GBT link.

Added:
>
>

DTM

Clocks

160MHz DTM reference clock.

This has the advantage that a PLL may not be needed since a simple clock divider can be used to generate the 40MHz clock. However, it comes with the disadvantage that the phase ambiguity of the VTRX 40MHz clock and the DTM 40 MHz clock must be resolved.

40MHz DTM reference clock.

A PLL is needed to generate a 160MHz clock but the 40MHz phase ambiguity is removed.

Phase aligned 160MHz and 40MHz reference clocks

This is not currently supported by the hardware. A future version could implement a second reference clock input to the DTM. Both 160MHz and 40MHz reference clocks would be driven from the TCM module and have a constant but programmable alignment.

e-link fine timing

The up e-links operate in 320Mb/s (160MHz DDR) mode. The GBTX receivers must be phase-aligned to the data for reliable transmission. The default settings do not appear to be optimal for the PDMDB. A phase shift of about 90deg seems to give good results. All used e-links should therefore have the value 3 written in the per-link phase alignment register. It is quite likely, though not yet established, that a common setting will work on all links on all boards.

It is not clear whether the GBTX manual correctly documents which registers correspond to which channels. However, as it appears that the same value can be used everywhere, it is OK to write the value into all the e-link phase alignment registers even for the inactive e-links.

Note that this adjustment does not resolve the 40MHz clock ambiguity. It is used only to centre the sampling clock in the centre of the stable data region.

40MHz clock ambiguity

Since the DTM e-links are operating as 8:1 serialisers, there is in principle an 8-fold ambiguity in the phase relative to the receiving 40MHz clock. This is reduced to a 4-fold ambiguity because the DTM 40MHz clock is aligned to the rising edge of the 160MHz reference clock. There is a therefore a 1-in-4 chance of hitting on the correct alignment every time the PDMDB clock divider is reset.

Since there are spare bits in the GBTX frame, the current phase alignment can be monitored by transmitting a fixed, 8-bit wide pattern (e.g. 00000001) and observing where the 1 appears in the byte at the receiver. This information can be used (with a suitable synchronous reset mechanism in the PDMDB) to allow the correct adjustment of the 40MHz clock phase at the transmitter. Another possibility is to exploit the fact that there is no phase ambiguity for the TFC commands received by the PDMDB FPGAs. The PDMDB can exploit this by aligning the 40MHz clock to the TFC command. This results in a deterministic phase relationship between the TCM and DTM 40 MHz clocks.

Revision 12017-04-04 - StephenWotton

Line: 1 to 1
Added:
>
>
META TOPICPARENT name="RichUpgradeElectronics"

PDMDB

The RICH PDMDB provides the configuration and data interface between the elementary cells and the LHCb readout system (or miniDAQ or RichMuDaq). The hardware is based on 3 Xilinx Kintex7 FPGAs that capture the FE data from the digital CLARO outputs and forward them to the readout sytstem via 3 DTM (Data Transmission Module) plug-ins that each implement two GBT links. The PDMDB is controlled through a TCM (Trigger and Control Module) plug-in that implements the LHCb configuration and fast control interface over one bi-directional GBT link.

 
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