Difference: BccChip (3 vs. 4)

Revision 42011-06-30 - SergioGonzalez

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The Buffer Control Chip Chip (BCC)

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The BCC chip collects and multiplexes the data from the two columns of one hybrid. Its main features are:
  • LVDS buffering
  • 40 MHZ BCO clock multiplier to get a 80 MHz DCLK
  • Config register, with readback
  • ABCN DCLK selectable as 40/80 MHz
  • Multiplexes
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The BCC chip receives as input the main BCO clock @40 MHz and it can deliver a 80 MHz DCLK. It then multiplexes the data coming from the two columns of one hybrid onto a 80/160 MHz data line (depending on the DCLK frequency selected, 40/80 MHz). The BCC has a 5-bit hardware address and one can perform read/write operations on its 16-bit configuration register. The BCC also receives a L1R signal which is de-multiplexed into the reset (RESETB) and trigger (L1) signals to be delivered to the ABCN chips. After a power-reset, the chip is disabled for 512 cycles of the BCO clock.

Some documentation and related links:

 
  • All clock signals are derived from the BCO input.
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  • The power-on reset disables the chip for 512 cycles of the BCO clock.
  • Each BCC has a hardware address that can be set on the ID0-ID5 inputs.
 
  • The BCC includes a header in the commands forwarded to the ABCN chips are . The BCC(s) concerned by this header forwards the payload to the ABCNs.
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  • It de-multiplexes the L1R signal into the reset and trigger signals.
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Config register, with read-back ABCN data clock (DCLK) selectable as 40 or 80MHz Multiplex 2 ABCN streams onto 80/160MHz data line L1 line multiplexed with RESETB (L1R) – separate decoder, provides BCC-RESET Programmable Clocks inversion ABCN data sync (“sample and hold”) (invertible) ABCN signals synchronised to BCO (invertible) No-MUX mode – single channel readout select Redundant ABCN data lines selectable Power-on Reset Quad-mode – mux all 4 data lines (low priority feature)

 
 
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