Difference: PulsariibTestingForMassProductionStage (1 vs. 7)

Revision 72016-04-19 - ZijunXu

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META TOPICPARENT name="HardwareWorkOfZijun"
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Checklist for new Pulsar IIb boards at mass production stage

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Device Number:

Inspector:

Line: 7 to 4
 

Device Number:

Inspector:

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Introduction

Useful links:

Added:
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Anti-Static

  • [ ] Before touching any boards/devices, using an anti-static wrist strap to keep your partner and yourself grounded;
  • [ ] When moving any boards/devices, using anti-static bags or boxes;

Top and back view

 

Visual Testing

  • [ ] (if you could) check the type of PFGA, this design supports four Xilinx FPGAs in the FFG1927 package:
    • XC7VX690T (80 GTX, be used in the first proto-type);
Line: 29 to 34
 
  • [ ] Measure the resistors which are involved with the Power Regulators :
    • All the resistors listed in the below table are in the back of pulsarIIb board:
    • resistor_distri.PNG
Changed:
<
<
    • Note, the observed values in the below table is from pulsarIIb #3, no need to be exactly same.
>
>
    • Note, the reference values in the below table is from pulsarIIb #3, no need to be exactly same.
 
    • RegulatorResistorvalue in schematics (Ω)reference value(Ω)observed (Ω)
      U16 R22 240 242
      R26 4.2k 4.19k
      R28 10k 10.05k
      R29 36.5k 36.2k
      U17 R23 240 242
      R27 30.0k 19.7k
      R30 23.7k 23.5k
      R31 23.7k 23.4k
      U18 R24 240 242
      R25 10k 8.88k
      R32 23.7k 23.5k
      R33 36.5k 36.4k
      U21 R34 240 242
      R36 30.0k 19.6k
      R38 36.5k 36.2k
      R39 23.7k 23.5k
      U23 R35 240 242
      R37 20.0k 15.8k
      R40 10k 10.05k
      R41 23.7k 23.5k
  • [ ] Dip Switch status (SW1,SW2):
    • Set the 2 dip switches to 200MHz

Revision 62016-04-19 - ZijunXu

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META TOPICPARENT name="HardwareWorkOfZijun"

Checklist for new Pulsar IIb boards at mass production stage

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Device Number:

Inspector:

 

Introduction

Useful links:

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Visual Testing

Line: 20 to 24
 
    • Soldering quality;
    • orientation of IC's: see small ticks around the IC's;
    • polarity of capacitors, see figure below:
Changed:
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    • polarized_Capacitors.PNG polarized_Capacitors2.PNG
>
>
    • polarized_Capacitors.PNGpolarized_Capacitors2.PNG
 
    • check all fuses are installed.
  • [ ] Measure the resistors which are involved with the Power Regulators :
    • All the resistors listed in the below table are in the back of pulsarIIb board:
Changed:
<
<
    • resistor_distri.PNG
>
>
    • resistor_distri.PNG
 
    • Note, the observed values in the below table is from pulsarIIb #3, no need to be exactly same.
Changed:
<
<
    • Regulator Resistor value in schematics (Ω)value to be observed (Ω)
      U16 R22 240 242
      R26 4.2k 4.19k
      R28 10k 10.05k
      R29 36.5k 36.2k
      U17 R23 240 242
      R27 30.0k 19.7k
      R30 23.7k 23.5k
      R31 23.7k 23.4k
      U18 R24 240 242
      R25 10k 8.88k
      R32 23.7k 23.5k
      R33 36.5k 36.4k
      U21 R34 240 242
      R36 30.0k 19.6k
      R38 36.5k 36.2k
      R39 23.7k 23.5k
      U23 R35 240 242
      R37 20.0k 15.8k
      R40 10k 10.05k
      R41 23.7k 23.5k
>
>
    • RegulatorResistorvalue in schematics (Ω)reference value(Ω)observed (Ω)
      U16 R22 240 242
      R26 4.2k 4.19k
      R28 10k 10.05k
      R29 36.5k 36.2k
      U17 R23 240 242
      R27 30.0k 19.7k
      R30 23.7k 23.5k
      R31 23.7k 23.4k
      U18 R24 240 242
      R25 10k 8.88k
      R32 23.7k 23.5k
      R33 36.5k 36.4k
      U21 R34 240 242
      R36 30.0k 19.6k
      R38 36.5k 36.2k
      R39 23.7k 23.5k
      U23 R35 240 242
      R37 20.0k 15.8k
      R40 10k 10.05k
      R41 23.7k 23.5k
 
  • [ ] Dip Switch status (SW1,SW2):
    • Set the 2 dip switches to 200MHz
Changed:
<
<
    • clock_sw12.PNG clock_setting.PNG
>
>
    • clock_sw12.PNGclock_setting.PNG
 
  • [] Check jumpers configuration:
    • Zone 1 jumper (JP2):
      • OFF = IPMC CONTROL; ON = FORCE 12V ON;
      • When there is no IPMC, turn on to force 12V on;
Changed:
<
<
      • jumper_zone1.png
>
>
      • jumper_zone1.png
 
    • 4 FMC jumpers (JP1-FMC1,2,3,4):
      • 1-2: BYPASS; 2-3: NORMAL;
      • when there is NO FMC mezzanine card, need to bypass this FMC connecter. 1 jumper as example:
Changed:
<
<
      • jumper_fmc.png jumper_fmc2.png
>
>
      • jumper_fmc.pngjumper_fmc2.png
 
    • Zone3 jumpers (JP3, JP4):
      • ON = IPMC CONTROL; OFF = FORCE ON; (opposite to Zone1 jumper JP2)
      • when there is no IPMC, OFF to force RTM power on:
Changed:
<
<
      • jumper_zone3.png
>
>
      • jumper_zone3.png
 
  • [ ] Put FPGA Heat Sink, and fan;

Voltages Testing

  • [ ] Use anti-static band to connect yourself with GND.
Line: 52 to 57
 
  • [ ] With mini backplane;
  • [ ] without RTM;
  • [ ] without FMC, JP1-FMC1,2,3,4 set to bypass(connect 1-2);
Added:
>
>
 At first, test management voltage:
  • [ ] Without IPMC mezzanine card, but turn JP2 off, so the 12V voltage are off, while the management voltage (3.3V from PIM) still on:
Changed:
<
<
  • valtage_pim3p3.PNG
>
>
  • valtage_pim3p3.PNG
 
  • [ ] After this test, turn off the main voltage.
Added:
>
>
 Then, test other voltages:
  • [ ] Check all jumpers' pin states again.
    • [ ] without IPMC mezzanine card, JP2 ON, JP3 OFF, JP4 OFF;
Line: 65 to 72
 
  • [ ] Check current value (before FPGA is programmed);
  • [ ] Probe voltage of several points to check if they are expected:
    • [ ] 5 test points of GND:
Changed:
<
<
    • GND.PNG
>
>
    • GND.PNG
 
    • Note: Summary of positions of power regulators:
Changed:
<
<
    • voltage_summary.PNG
>
>
    • voltage_summary.PNG
 
    • [ ] VCC12 (from Power Converter U9): input for U16, U17, U18, U21, and U23;
      • U16: C103, C104
Changed:
<
<
      • valtage_12_U16.PNG
>
>
      • valtage_12_U16.PNG
 
      • U17: C115, C117, and C118; U18: C110 and C111; U21: C107 and C108;
Changed:
<
<
      • valtage_12_U171821.PNG
>
>
      • valtage_12_U171821.PNG
 
      • U23: C119, C121,and C122;
Changed:
<
<
      • valtage_12_U23.PNG
>
>
      • valtage_12_U23.PNG
 
    • [ ] VCC3V3: testing point (output of U16, 20A)
Changed:
<
<
    • valtage_3p3_U16.PNG
>
>
    • valtage_3p3_U16.PNG
 
    • [ ] VCC1V0 testing point(VCCINT, CVVBRAM, output of U17, 40A)
Changed:
<
<
    • valtage_1_U17.PNG
>
>
    • valtage_1_U17.PNG
 
    • [ ] VCC1V0 : testing point (MGTVACC, output of U21, input of FPGA, 40A):
Changed:
<
<
    • valtage_1_U21.PNGvaltage_1p0_fpga.PNG
>
>
    • valtage_1_U21.PNGvaltage_1p0_fpga.PNG
 
    • [ ] VCC1V2 :testing point (MGTATT, output of U23, 20A):
Changed:
<
<
    • valtage_1p2_U23.PNG
>
>
    • valtage_1p2_U23.PNG
 
    • [ ] VCC1V8 : testing point (VCCAUX, VCCO, VCCAUX_IO, output of U18, input of FPGA, 6A)
Changed:
<
<
    • valtage_1p8_U18.PNGvaltage_1p8_fpga.PNG
>
>
    • valtage_1p8_U18.PNGvaltage_1p8_fpga.PNG
 
    • [ ] VCC1V5 (VCCO, DDR3, output of U22, input of FPGA, 3A)
Changed:
<
<
    • valtage_1p5_fpga.PNG
>
>
    • valtage_1p5_fpga.PNG
 
    • [ ] VCC1V8 (MGTVCCAUX, output of U29, 3A)
    • Note: this pin should be probed, be careful not to have short circuit!!)
Changed:
<
<
    • valtage_1p8_U29.PNG
>
>
    • valtage_1p8_U29.PNG
 
  • [ ] Clock probing points::
    • SYSCLOCK (X5), 200 MHz (5ns period);
Changed:
<
<
    • Clock_X5.PNG
>
>
    • Clock_X5.PNG
 
    • crystal oscillator (25MHz) {X1, X2};
Changed:
<
<
    • Clock_X1.PNG Clock_X2.PNG
>
>
    • Clock_X1.PNG Clock_X2.PNG

 

Insert IPMC card: manager

After make sure the board passed all voltage testing, we could insert IPMC card and pull out J2 jumper.

Line: 103 to 109
 
  • [ ] Probe the power output from Pulsar IIb board zone-3:
    • 12V@ D10
Changed:
<
<
    • rtm_power.png
>
>
    • rtm_power.png
 
    • 12V power and 3.3V manage power @ blue connector:
Changed:
<
<
      • Only probe the orange pins, not touch the black pins;
>
>
      • Only probe the orange pins, not touch the black pins;
 
          • A1: 0V. It's Manage Power, only when RTM connected, it's 3.3V;
          • A2: GND;
Line: 120 to 126
 
          • C1: SCL_L
          • C2: SDA_L
          • C3, C4, D1, D2, D3, D4 are not used
Changed:
<
<
      • rtm_connector.pngrtm_power2.png
>
>
      • rtm_connector.pngrtm_power2.png
 
  • [ ] Connect the RTM to Pulsar IIb board to further testing

First LED Blinking Test

  • [ ] Check 4 FMC jumpers( JP1-FMC1,2,3,4) connection before JTAG programming: if there is no FMC card, to connect 1-2 to bypass this FMC connector.
Changed:
<
<
  • [ ] Programming FPGA with LED blinker (link) from JTAG programming header:
>
>
  • [ ] Programming FPGA with LED blinker ( link) from JTAG programming header:
 
    • [ ] Check DONE LED( D1): turn Blue with vivado XADC can be monitered.
Changed:
<
<
      • FPGA_Done.png
>
>
      • FPGA_Done.png
 
    • [ ] Take care for temperature when you program new firmware ALWAYS (SET 75C^o as up limit).
    • [ ] There are four LEDs in frond panel, if input clock frequency is A MHz, for example 200 MHz:
      • 1st LED : A*1e6/2^(25+1) = 2.98 Hz blinking
Line: 137 to 143
 
Picture below shows GTHs connected to the QSFP+ and SFP+ modules in the RTM. (213-2 and 111-1 are not connected)
Changed:
<
<
GTH_in_RTM.PNG
>
>
GTH_in_RTM.PNG
  28 GTHs used for Fabric Interface (Backplane): GTX111-2 to GTX118-1. In new mini-backplane, GTX118-1 is connected to SFP+ connector, other are looped back.
Line: 172 to 178
 
  • [ ] Note: Start from small number of GTHs and low speed:
  • [ ] Note: need to go through all the steps for first board. for other boards, items in red color is needed.
Changed:
<
<
      • [ ] 6Gbps 4 GTHs (Quad 116, Fabric): firmware
      • [ ] 6Gbps 8 GTHs (Quad 117,118, Fabric): firmware
      • [ ] 6Gbps 20 GTHs (Quad 112-116, Fabric): firmware
      • [ ] 6Gbps 44 GTHs (Quad 110, 111, 210 - 218, include all RTM links): firmware
      • [ ] 8Gbps 44 GTHs (Quad n111-119,218,219, include all Fabric links): firmware
      • [ ] 6Gbps 80 GTHs (all Quad): firmware
      • [ ] 8Gbps 80 GTHs (all Quad): firmware
      • [ ] 10Gbps 80 GTHs (all Quad): firmware
>
>
      • [ ] 6Gbps 4 GTHs (Quad 116, Fabric): firmware
      • [ ] 6Gbps 8 GTHs (Quad 117,118, Fabric): firmware
      • [ ] 6Gbps 20 GTHs (Quad 112-116, Fabric): firmware
      • [ ] 6Gbps 44 GTHs (Quad 110, 111, 210 - 218, include all RTM links): firmware
      • [ ] 8Gbps 44 GTHs (Quad n111-119,218,219, include all Fabric links): firmware
      • [ ] 6Gbps 80 GTHs (all Quad): firmware
      • [ ] 8Gbps 80 GTHs (all Quad): firmware
      • [ ] 10Gbps 80 GTHs (all Quad): firmware
 -- Main.ZijunXu - 25 Jun 2014 \ No newline at end of file

Revision 52014-07-11 - ZijunXu

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META TOPICPARENT name="HardwareWorkOfZijun"
Changed:
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Pulsar IIb checking list for mass production stage

>
>

Checklist for new Pulsar IIb boards at mass production stage

 

Introduction

Useful links:

Revision 42014-07-07 - ZijunXu

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META TOPICPARENT name="HardwareWorkOfZijun"
Line: 171 to 171
 
  • [ ] Note: always checking current and temperature when increasing number of GTHs;
  • [ ] Note: Start from small number of GTHs and low speed:
  • [ ] Note: need to go through all the steps for first board. for other boards, items in red color is needed.
Changed:
<
<
      • [ ] 6Gbps 4 GTHs (Quad 116): firmware
      • [ ] 6Gbps 8 GTHs (Quad 117,118): firmware
      • [ ] 6Gbps 20 GTHs (Quad 112-116): firmware
>
>
      • [ ] 6Gbps 4 GTHs (Quad 116, Fabric): firmware
      • [ ] 6Gbps 8 GTHs (Quad 117,118, Fabric): firmware
      • [ ] 6Gbps 20 GTHs (Quad 112-116, Fabric): firmware
 
      • [ ] 6Gbps 44 GTHs (Quad 110, 111, 210 - 218, include all RTM links): firmware
      • [ ] 8Gbps 44 GTHs (Quad n111-119,218,219, include all Fabric links): firmware
      • [ ] 6Gbps 80 GTHs (all Quad): firmware

Revision 32014-06-25 - ZijunXu

Line: 1 to 1
 
META TOPICPARENT name="HardwareWorkOfZijun"
Line: 96 to 96
 
    • crystal oscillator (25MHz) {X1, X2};
    • Clock_X1.PNG Clock_X2.PNG
Added:
>
>

Insert IPMC card: manager

After make sure the board passed all voltage testing, we could insert IPMC card and pull out J2 jumper.

 

RTM power supply test

  • [ ] Probe the power output from Pulsar IIb board zone-3:
Line: 166 to 169
 FPGA IBERT testing:
  • [ ] Check the 2 clocks setting: 200 MHz
  • [ ] Note: always checking current and temperature when increasing number of GTHs;
Changed:
<
<
  • [ ] Start from small number of GTHs and low speed:
      • [ ] 6Gbps 4 GTHs (Guad 116): firmware
      • [ ] 6Gbps 8 GTHs (Guad 117,118): firmware
      • [ ] 6Gbps 20 GTHs (Guad 112-116): firmware
      • [ ] 6Gbps 44 GTHs (110, 111, 210 - 218, include all RTM links): firmware
      • [ ] 8Gbps 44 GTHs (111-119,218,219, include all Fabric links): firmware
      • [ ] 6Gbps 80 GTHs (all Guad): firmware
      • [ ] 8Gbps 80 GTHs (all Guad): firmware
      • [ ] 10Gbps 80 GTHs (all Guad): firmware
>
>
  • [ ] Note: Start from small number of GTHs and low speed:
  • [ ] Note: need to go through all the steps for first board. for other boards, items in red color is needed.
      • [ ] 6Gbps 4 GTHs (Quad 116): firmware
      • [ ] 6Gbps 8 GTHs (Quad 117,118): firmware
      • [ ] 6Gbps 20 GTHs (Quad 112-116): firmware
      • [ ] 6Gbps 44 GTHs (Quad 110, 111, 210 - 218, include all RTM links): firmware
      • [ ] 8Gbps 44 GTHs (Quad n111-119,218,219, include all Fabric links): firmware
      • [ ] 6Gbps 80 GTHs (all Quad): firmware
      • [ ] 8Gbps 80 GTHs (all Quad): firmware
      • [ ] 10Gbps 80 GTHs (all Quad): firmware
 -- Main.ZijunXu - 25 Jun 2014

Revision 22014-06-25 - ZijunXu

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META TOPICPARENT name="HardwareWorkOfZijun"
Line: 6 to 6
 

Introduction

Useful links:

Added:
>
>
 
Deleted:
<
<
 

Visual Testing

  • [ ] (if you could) check the type of PFGA, this design supports four Xilinx FPGAs in the FFG1927 package:
    • XC7VX690T (80 GTX, be used in the first proto-type);
Line: 163 to 163
 
GTX119_2 (FMC) R -
GTX119_3 (FMC) - R
Changed:
<
<
FPGA IBERT testing start:
>
>
FPGA IBERT testing:
 
  • [ ] Check the 2 clocks setting: 200 MHz
  • [ ] Note: always checking current and temperature when increasing number of GTHs;
Changed:
<
<
  • [ ] IBERT firmwares

Pulsar Vidado (Y/N) # of channels Channels Usage Speed (Gbps) Speed (Gbps) Speed (Gbps) Speed (Gbps)
IIb Y 4 with CPLL 116 Fabric [ 3] [ 6] [ 8] [ 10]
IIb Y 8 with CPLL 117, 118 Fabric 3 [ 6] 8 10
IIb Y 20 with CPL 112 - 116 Fabric 3 [ 6] 8 10
IIb Y 24 with CPLL 213 - 218 RTM 3 [ 6] 8 10
IIb Y 24 with CPLL 110, 111, 210 - 213 RTM 3 [ 6] 8 10
IIb Y 44 with CPLL 111 - 119, 218, 219 Fabric [ 3]     [ 10]
IIb Y 44 with QPLL 111 - 119, 218, 219 Fabri     [ 8] [ 10]
IIb Y 44 with CPLL 110, 111, 210 - 218 RTM [ 3] [ 6] [ 8] [ 10]
IIb y 44 with QPLL 110, 111, 210 - 218 RTM     [ 8] [ 10]
IIb Y 80 with CPLL   All [ 3] [ 6] [ 8] [ 10]
IIb Y 80 with QPLL   All       [ 10]
IIb N 20 with CPLL 112 - 116 Fabric [ 3] [ 6] [ 8] [ 10]
IIa N 1 with CPLL GTX12 Fabric [ 3] [ 6] [ 8] [ 10]
IIa Y( only work in Vivado) 4 with CPLL GTX12 - GTX15 Fabric [ 3] [ 6] [ 8] [ 10]
>
>
  • [ ] Start from small number of GTHs and low speed:
      • [ ] 6Gbps 4 GTHs (Guad 116): firmware
      • [ ] 6Gbps 8 GTHs (Guad 117,118): firmware
      • [ ] 6Gbps 20 GTHs (Guad 112-116): firmware
      • [ ] 6Gbps 44 GTHs (110, 111, 210 - 218, include all RTM links): firmware
      • [ ] 8Gbps 44 GTHs (111-119,218,219, include all Fabric links): firmware
      • [ ] 6Gbps 80 GTHs (all Guad): firmware
      • [ ] 8Gbps 80 GTHs (all Guad): firmware
      • [ ] 10Gbps 80 GTHs (all Guad): firmware
 -- Main.ZijunXu - 25 Jun 2014

Revision 12014-06-25 - ZijunXu

Line: 1 to 1
Added:
>
>
META TOPICPARENT name="HardwareWorkOfZijun"

Pulsar IIb checking list for mass production stage

Introduction

Useful links:

Visual Testing

  • [ ] (if you could) check the type of PFGA, this design supports four Xilinx FPGAs in the FFG1927 package:
    • XC7VX690T (80 GTX, be used in the first proto-type);
    • XC7VX550T (80 GTX);
    • XC7VX485T (56 GTX, Quads 113-119 & 213-219)
    • XC7VX415T (48 GTX, Quads 114-119 & 214-219)

  • [ ] Check if all the component soldered properly, and in correct orientation:
    • Soldering quality;
    • orientation of IC's: see small ticks around the IC's;
    • polarity of capacitors, see figure below:
    • polarized_Capacitors.PNG polarized_Capacitors2.PNG
    • check all fuses are installed.
  • [ ] Measure the resistors which are involved with the Power Regulators :
    • All the resistors listed in the below table are in the back of pulsarIIb board:
    • resistor_distri.PNG
    • Note, the observed values in the below table is from pulsarIIb #3, no need to be exactly same.
    • Regulator Resistor value in schematics (Ω)value to be observed (Ω)
      U16 R22 240 242
      R26 4.2k 4.19k
      R28 10k 10.05k
      R29 36.5k 36.2k
      U17 R23 240 242
      R27 30.0k 19.7k
      R30 23.7k 23.5k
      R31 23.7k 23.4k
      U18 R24 240 242
      R25 10k 8.88k
      R32 23.7k 23.5k
      R33 36.5k 36.4k
      U21 R34 240 242
      R36 30.0k 19.6k
      R38 36.5k 36.2k
      R39 23.7k 23.5k
      U23 R35 240 242
      R37 20.0k 15.8k
      R40 10k 10.05k
      R41 23.7k 23.5k
  • [ ] Dip Switch status (SW1,SW2):
    • Set the 2 dip switches to 200MHz
    • clock_sw12.PNG clock_setting.PNG
  • [] Check jumpers configuration:
    • Zone 1 jumper (JP2):
      • OFF = IPMC CONTROL; ON = FORCE 12V ON;
      • When there is no IPMC, turn on to force 12V on;
      • jumper_zone1.png
    • 4 FMC jumpers (JP1-FMC1,2,3,4):
      • 1-2: BYPASS; 2-3: NORMAL;
      • when there is NO FMC mezzanine card, need to bypass this FMC connecter. 1 jumper as example:
      • jumper_fmc.png jumper_fmc2.png
    • Zone3 jumpers (JP3, JP4):
      • ON = IPMC CONTROL; OFF = FORCE ON; (opposite to Zone1 jumper JP2)
      • when there is no IPMC, OFF to force RTM power on:
      • jumper_zone3.png
  • [ ] Put FPGA Heat Sink, and fan;

Voltages Testing

  • [ ] Use anti-static band to connect yourself with GND.
  • [ ] Setup the mini backplan with proper voltage applied.(recommend 48V , can work from 36V to 72V, )
  • [ ] Turn on the fan for cooling.
Initial configuration for the first testing:
  • [ ] With mini backplane;
  • [ ] without RTM;
  • [ ] without FMC, JP1-FMC1,2,3,4 set to bypass(connect 1-2);
At first, test management voltage:
  • [ ] Without IPMC mezzanine card, but turn JP2 off, so the 12V voltage are off, while the management voltage (3.3V from PIM) still on:
  • valtage_pim3p3.PNG
  • [ ] After this test, turn off the main voltage.
Then, test other voltages:
  • [ ] Check all jumpers' pin states again.
    • [ ] without IPMC mezzanine card, JP2 ON, JP3 OFF, JP4 OFF;
  • [ ] Turn on the main voltage.
    • Note: immediately 12V will be on and all the voltage will be activated;
    • Note: hot swap handle not work in this version of design!! Turn off the main voltage directly to turn off the board.
  • [ ] Check current value (before FPGA is programmed);
  • [ ] Probe voltage of several points to check if they are expected:
    • [ ] 5 test points of GND:
    • GND.PNG
    • Note: Summary of positions of power regulators:
    • voltage_summary.PNG
    • [ ] VCC12 (from Power Converter U9): input for U16, U17, U18, U21, and U23;
      • U16: C103, C104
      • valtage_12_U16.PNG
      • U17: C115, C117, and C118; U18: C110 and C111; U21: C107 and C108;
      • valtage_12_U171821.PNG
      • U23: C119, C121,and C122;
      • valtage_12_U23.PNG
    • [ ] VCC3V3: testing point (output of U16, 20A)
    • valtage_3p3_U16.PNG
    • [ ] VCC1V0 testing point(VCCINT, CVVBRAM, output of U17, 40A)
    • valtage_1_U17.PNG
    • [ ] VCC1V0 : testing point (MGTVACC, output of U21, input of FPGA, 40A):
    • valtage_1_U21.PNGvaltage_1p0_fpga.PNG
    • [ ] VCC1V2 :testing point (MGTATT, output of U23, 20A):
    • valtage_1p2_U23.PNG
    • [ ] VCC1V8 : testing point (VCCAUX, VCCO, VCCAUX_IO, output of U18, input of FPGA, 6A)
    • valtage_1p8_U18.PNGvaltage_1p8_fpga.PNG
    • [ ] VCC1V5 (VCCO, DDR3, output of U22, input of FPGA, 3A)
    • valtage_1p5_fpga.PNG
    • [ ] VCC1V8 (MGTVCCAUX, output of U29, 3A)
    • Note: this pin should be probed, be careful not to have short circuit!!)
    • valtage_1p8_U29.PNG
  • [ ] Clock probing points::
    • SYSCLOCK (X5), 200 MHz (5ns period);
    • Clock_X5.PNG
    • crystal oscillator (25MHz) {X1, X2};
    • Clock_X1.PNG Clock_X2.PNG

RTM power supply test

  • [ ] Probe the power output from Pulsar IIb board zone-3:
    • 12V@ D10
    • rtm_power.png
    • 12V power and 3.3V manage power @ blue connector:
      • Only probe the orange pins, not touch the black pins;
          • A1: 0V. It's Manage Power, only when RTM connected, it's 3.3V;
          • A2: GND;
          • A3: 12V;
          • A4: GND;
          • B2: 3.3V(PNs) when RTM is disconnected;
          • B3: 12V;
          • B4: GND
      • black pins:
          • B1: ENABLEn
          • C1: SCL_L
          • C2: SDA_L
          • C3, C4, D1, D2, D3, D4 are not used
      • rtm_connector.pngrtm_power2.png
  • [ ] Connect the RTM to Pulsar IIb board to further testing

First LED Blinking Test

  • [ ] Check 4 FMC jumpers( JP1-FMC1,2,3,4) connection before JTAG programming: if there is no FMC card, to connect 1-2 to bypass this FMC connector.
  • [ ] Programming FPGA with LED blinker (link) from JTAG programming header:
    • [ ] Check DONE LED( D1): turn Blue with vivado XADC can be monitered.
      • FPGA_Done.png
    • [ ] Take care for temperature when you program new firmware ALWAYS (SET 75C^o as up limit).
    • [ ] There are four LEDs in frond panel, if input clock frequency is A MHz, for example 200 MHz:
      • 1st LED : A*1e6/2^(25+1) = 2.98 Hz blinking
      • 2nd LED: A*1e6/2^(26+1) = 1.49 Hz blinking
      • 3rd LED : A*1e6/2^(27+1) =0.745 Hz blinking
      • 4th LED : always on. (It's clock locked signal: if the sys-clock properly worked, alwyas on. )

IBERT Test


Picture below shows GTHs connected to the QSFP+ and SFP+ modules in the RTM. (213-2 and 111-1 are not connected)

GTH_in_RTM.PNG

28 GTHs used for Fabric Interface (Backplane): GTX111-2 to GTX118-1. In new mini-backplane, GTX118-1 is connected to SFP+ connector, other are looped back.

12(=3x4) GTHs used for FMC cards(1 to 4) are: [219-3,219-2,219-1], [219-0, 218-3,218-2], [118-2,118-3,119-0], [119-1,119-2,119-3];

Summary of the GTH channals have been reversed: ("R"=reversed, "-" = normal )

GTH TX RX
GTX211_2 (RTM) R -
GTX212_2 (RTM) - R
GTX212_3 (RTM) R -
GTX214_0 (RTM) - R
GTX218_3 (FMC) R -
GTX219_1 (FMC) - R
GTX219_2 (FMC) - R
GTX219_3 (FMC) R R
     
GTX110_0 (RTM) R R
GTX110_1 (RTM) R R
GTX110_2 (RTM) R R
GTX110_3 (RTM) R R
GTX111_0 (RTM) R -
GTX111_2 (fab) R -
GTX114_3 (fab) - R
GTX118_2 (FMC) - R
GTX119_1 (FMC) R R
GTX119_2 (FMC) R -
GTX119_3 (FMC) - R

FPGA IBERT testing start:

  • [ ] Check the 2 clocks setting: 200 MHz
  • [ ] Note: always checking current and temperature when increasing number of GTHs;
  • [ ] IBERT firmwares

Pulsar Vidado (Y/N) # of channels Channels Usage Speed (Gbps) Speed (Gbps) Speed (Gbps) Speed (Gbps)
IIb Y 4 with CPLL 116 Fabric [ 3] [ 6] [ 8] [ 10]
IIb Y 8 with CPLL 117, 118 Fabric 3 [ 6] 8 10
IIb Y 20 with CPL 112 - 116 Fabric 3 [ 6] 8 10
IIb Y 24 with CPLL 213 - 218 RTM 3 [ 6] 8 10
IIb Y 24 with CPLL 110, 111, 210 - 213 RTM 3 [ 6] 8 10
IIb Y 44 with CPLL 111 - 119, 218, 219 Fabric [ 3]     [ 10]
IIb Y 44 with QPLL 111 - 119, 218, 219 Fabri     [ 8] [ 10]
IIb Y 44 with CPLL 110, 111, 210 - 218 RTM [ 3] [ 6] [ 8] [ 10]
IIb y 44 with QPLL 110, 111, 210 - 218 RTM     [ 8] [ 10]
IIb Y 80 with CPLL   All [ 3] [ 6] [ 8] [ 10]
IIb Y 80 with QPLL   All       [ 10]
IIb N 20 with CPLL 112 - 116 Fabric [ 3] [ 6] [ 8] [ 10]
IIa N 1 with CPLL GTX12 Fabric [ 3] [ 6] [ 8] [ 10]
IIa Y( only work in Vivado) 4 with CPLL GTX12 - GTX15 Fabric [ 3] [ 6] [ 8] [ 10]

-- Main.ZijunXu - 25 Jun 2014

 
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