Latest firmware versions

• Processing FPGA firmware

  Version number	x20B
  Version register value	x20B
  Last update of vhdl source	23 Apr 2009
  Programming (.bit) file generation	17 June 2009
  Last modification	Implemented unique table of parameters for the fastor logic block; modifed fastor_logic.vhd and processing_registers.vhd
  Xilinx Project location	pcphed08 E:\gaglieri_local\work\electronic_projects\pixel_trigger\proc_fpga_firmware
  Xilinx project archive	https://edms.cern.ch/nav/CERN-0000006814/CERN-0000076367

• Control FPGA firmware

  Version number	x104
  Version register value	x104
  Last update of vhdl source	17 Jun 2008
  Programming (.bit) file generation	17 Jun 2009
  Last modification	Slowed down the I2C player to make the control of the TTCrx working
  Xilinx Project location	pcphed08 E:\gaglieri_local\work\electronic_projects\pixel_trigger\control_fpga_firmware
  Xilinx project archive	https://edms.cern.ch/nav/CERN-0000006814/CERN-0000076367

• OPTIN FPGA firmware

  Version number	x105
  Version register value	x105
  Last update of vhdl source	June 2009
  Programming (.bit) file generation	16 June 2009
  Last modifications	Added test pulse timestamping, self-masking. Modified optin_registers and extractor
  Xilinx Project location	pcphed08 E:\gaglieri_local\work\electronic_projects\pixel_trigger\optin_fpga_firmware
  Xilinx project archives	https://edms.cern.ch/nav/CERN-0000006814/CERN-0000076367

Functionalities to implement

• (TO DO) Self masking of FO during readout
• (TO DO) Change addressing procedure to use the data bus during addressing instead of the address bus
• (TO DO) Add timeout protection or watchdogs in all state machines
  • Control FPGA
  • Processing FPGA
  • OPTIN FPGA
• (TO DO) Test the remote programming of the OPTIN fpgas.
• (TO DO) FO pulses length real time histogramming
• (TO DO) Snapshot memory functionality
  • (TO DO) Add blocks implemented by Calogero
• (DONE 26/06/2007) Modify Processing FPGA firmware to have the signatures hardwired in the fastor logic block.
• (DONE) Modify firmware for each OPTIN channel for the (optional) self masking of double pulses to mask long pulses
• (DONE) Add timestamping on the Test Pulse (TP) feedback signal: add register into timestamping.vhd; connect to timestamp_2 output port of link.vhd; connect to optin_registers.
• (DONE) The processing fpga code has to be modified such that there is only ONE file used to define the algorithms, the meaning of parameters, the names, the version of the firmware
• (DONE) Change the register used to select the cosmic trigger logic, choose one of the registers from the table of parameters
• (DONE) Remote reconfiguration of Processing FPGA
  • (DONE) Implement blocks to execute Xilinx ACE files
• (DONE) Processing FPGA registers block
• (DONE) Processing FPGA counters for Fast-OR lines self testing
• (DONE) Registers in the CONTROL FPGA
  • (DONE) registers for the OPTIN fpgas programming "DONE" signals
  • (DONE) status of QPLL and TTCrx chips
• Parity checking functionality completion and verification
  • (DONE) Processing FPGFA
  • (DONE) OPTIN FPGA
• Counters start/stop commands
  • (DONE) in the PROCESSING
  • (DONE) in the OPTIN
• TTCrx and QPLL
  • (DONE) Setting the delay register of the TTCrx by I2C interface
  • (DONE) reset command, solve the problem of clock stability after receiving the TTCinit command

• Timestamping
  • (TO DO) in the PROCESSING
  • (DONE) in the OPTIN
• (DONE) COmmand to reset the OPTIN boards settings
• (DONE) Fast-OR processing block in Processing FPGA
  • (DONE) Coincidence logic between top outer, top inner, bottom inner, bottom outer layer for cosmics
  • (DONE) Multiplicity algorithms
• (DONE) Main output block with compliance to CTP requirements (normal, random, signature, toggling)
• Trigger outputs
  • (DONE) Masking
  • (DONE) Dynamic programmability of output number 9
  • (NOT REQUIRED) Optional self masking of the output during the chip readout
  • (NOT REQUIRED) Function for the (optional) time extension of the Fast-OR pulse length to fix timing problems

Problems, bugs to fix, other things to implement

• (TO DO) BUG in the processing fpga firmware. An error in communication is observed when issuing the command: memory_access_test 16 0x1FFF000 0x1FFFFFF 3 1. This is a non existing area of the processing sram space. The control fpga state machine and the processing fpga state machine are stucked. Needs a hardware reset. See logbook file from 26/01/2009.
• (TO DO) Counter of the output is not masked when the output is masked
• (TO DO) Implement the delay function in the extractor by RAM based fifo instead of dedicated registers
• (DONE) BUG to solve: sometimes the command "start_programmer" does not work on the first issuing.
• (DONE) Replace the XIlinx Fifo core in the Control FPGA project with standard synthesizable VHDL description
• (DONE) Replace the Xilinx clock_buffering.xaw file in the three FPGAs with standard synthesizable VHDL description, compatible with simulation

• Communication bus
  • (TO DO) Propagation delay from clock to irdy_i signal in control FPGA to be reduced, rewrite bus_master state machine with different syntax
  • Bus turnaround state
    • (DONE) Processing FPGA code
    • (DONE) OPTIN FPGA code
    • (DONE) FIFO implementation for memory access in processing FPGA
    • (DONE) Correct target state machine for reading block phase
  • (DONE) Problem with parity checking when reading blocks of length 2 from OPTIN boards

• (DONE) Eliminate pad to pad path in processing FPGFA, time constraints failing

• (DONE) Timing refinement: add 1 ns to the processing DCM phase delay to center the processing FPGA clock phase wrt the OTPIN boards clock phases