SPD Router Wiki Page

link to Router alice1.web.cern.ch/alice1

This is a simple page to provide easy access to documentation on the Router for the SPD ALICE.


1.) First draft of SPD Router specification. ([[http://alice1.web.cern.ch/alice1/Router/SPD_Router_specification.pdf] [PDF format]])

2.) Schematics capture of SPD Router ([[][EDA-00589-V3]] EDA-00589-V2 EDA-00589_V1)

3.) PCB layout of SPD Router (EDA-00589-V3 EDA-00589-V2 EDA-00589_V1)

4.) Front Panel drawing of SPD Router (EDA-00589-V3)

General router web page: http://mkrivda.web.cern.ch/mkrivda/spd_router.htm

Registers in Router http://mkrivda.web.cern.ch/mkrivda/SPD_Router_registers.pdf

Programming routers and link receivers http://mkrivda.web.cern.ch/mkrivda/JAM_file_instructions.pdf

Programming Files

a) Router_fpga ver.1 (JAM file) - start number of versions

b) Router_fpga ver.2 (JAM file) - added temp interlock functionality

c) Router_fpga ver.3 (JAM file) - improved address counter for 6 channels

d) Router_fpga ver.4 (JAM file) - added BUSY from vme bus (control reg), delay for sequencer is set to 400us

e) Router_fpga ver.5 (JAM file) - improved start address fifo

f) Router_fpga ver.6 (JAM file) - added fast-or functionality

g) Router_fpga ver.7 + LinkRx_fpga ver.5 (JAM file for FPGAs, JAM file for FLASHs) - resets for fifo_start_address and fifo_end_address replaced by flash_dpm, improved Verilog code for output from fifos (for Quartus !), improved state machine for decoding L0 and L1 from TTCrx chip.

Production of SPD Routers

9U/6U VME Router crates definition


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Topic revision: r4 - 2008-06-09 - AlexanderKluge
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