Rx Card Version 31: not released yet, added recover from overflow functionality. set at bit2 of cntl0 and cntl1 to activate (address 19'h0, 19'h1), chan0 and 1 can only be switched on simultaneously. default is disabled. Once the fifo is filled to 500 entries, the data decoder is forced to read one 16 bit pixel chip line per clock cycle and decodes maximal one hit in this line and sends it to the DPM. The procedure is continued until the fifo has only 100 entries and the data decoding continues normally. For each event where at least one line is modified bit0 in the error word in the event description ram (last value of 4 entries) is activated. Additionally for each chip where data loss occured the error bit in the chip trailer (bit12) is activated.

Reg cntl0 and cntl1 increased to 5 bits.

The fastor_bit_mask has and the fastor_cnt0 and fastor_cnt1 have been removed.


Rx Card Version 30: not released yet, is functionally identically to Version 29 but unused logic is removed and warning in synplify are cleared. reg cntl0, cntl1 are 4 bit long only, bit 3:2 are channel id, bit 1 disable laser, bit 0 is test_writeenable


Rx Card Version 29: August 18, 2008, builds up on Version 27 but includes fastOr Extractor.

with this release of the SPD FPGA firmware (rxcard V29) the data stream written to the DAQ contains the information of the fastOr bit of each chip present in the readout. The data will be located in the so called chip trailer. For more information about the data format, please refer to the following document: http://akluge.home.cern.ch/akluge/work/alice/spd/spd_documents/SPDdataFormat.pdf

On the hardware side we need to set a delay register indicating the delay between the arrival of the fastOr bit from the detector in the rxcard and the arrival of the L1 signal from the TTC/router in the rxcard. The register fastor_l1_delay is on rxcard address h19 bits [6:0] and sets this delay, the default is: d70. The time delay can be measured automatically: a fastOr must be initiated (testPulse, cosmics, beam) and the SPD must be triggered either by PIT (cosmics or beam) or any particle trigger. The fastOrs of the two half staves connected to the rxcards are Ored, (thus they must be fastOr tuned and noise free) and the time between the Ored fastor signals and the next L1 is measured. This assumes that cable delays of two half staves on one rxcard are identical. The counter is updated after each L1 trigger. The same register 'fastor_l1_delay' bits [14:8] reads this delay value, which should be written into bits [6:0].

FastOr bit is sent in trailer bit 13 of each chip, bit 12 is error bit (always 0), bit 11:0 is hit per chip count. Register fastor_l1_delay on rx address h19 sets the delay between fastOr arrival and L1 arrival in rx card, default is: d70


Rx Card Version 28: July 14 2008, not yet released, gives busy upon vme_reset on channels 2,3,4.

with this release of the SPD FPGA firmware (rxcard V28) the data stream written to the DAQ will contain the information of the fastOr bit of each chip present in the readout. The data will be located in the so called chip trailer. For more information about the data format, please refer to the following document: http://akluge.home.cern.ch/akluge/work/alice/spd/spd_documents/SPDdataFormat.pdf

On the hardware side we need to set a delay register indicating the delay between the arrival of the fastOr bit from the detector in the rxcard and the arrival of the L1 signal from the TTC/router in the rxcard. The register fastor_l1_delay is on rxcard address h19 bits [6:0] and sets this delay, the default is: d70. The time delay can be measured automatically: a fastOr must be initiated (testPulse, cosmics, beam) and the SPD must be triggered either by PIT (cosmics or beam) or any particle trigger. The fastOrs of the two half staves connected to the rxcards are Ored, (thus they must be fastOr tuned and noise free) and the time between the Ored fastor signals and the next L1 is measured. This assumes that cable delays of two half staves on one rxcard are identical. The counter is updated after each L1 trigger. The same register 'fastor_l1_delay' bits [14:8] reads this delay value, which should be written into bits [7:0].

FastOr bit is sent in trailer bit 13 of each chip, bit 12 is error bit (always 0), bit 11:0 is hit per chip count. Register fastor_l1_delay on rx address h19 sets the delay between fastOr arrival and L1 arrival in rx card, default is: d57

reg cntl0, cntl1 are 4 bit long only, bit 3:2 are channel id, bit 1 disable laser, bit 0 is test_writeenable


Rx Card Version 27: July 1 2008

busy_mux changed and output of busy for channels 0-5 on indications 0 - 5. fastOr removed from indications


Rx Card Version 26: May 26 2008

rx_control: address decoder-> removed priority encoder in address decoder and some not used registers. //AK 2008 05 26 comm_sync_reg moved to rx_control as to have only one common block


Rx Card Version 25: 2008 05 22 contains commented fastOrExtractor, same number of cells and memory 79%/21% as before change 1124, f25 = 41.3, f1124=41.92 after changes as seen below 77%CLB/19% memory/38.5 MHz new compilation runs at faster than 40 MHz assign status0 = {7'b0, //in reset or startup condition all bits should be '0'

//Bit 24: rx_error_reg[1],

//Bit 23: rx_error[0],

//Bit 22: ~rx_ready[0],

//Bit 21: ~sigdet[0],

//Bit 20: seu_error[0],

//Bit 19: dpm_almost_full[0],

//Bit 18: ~pixel_fifo_empty[0],

//Bit 17: ~event_fifo_empty[0],

//BUSY bits************************************************************

//Bit 16: busy_mcm[0],

//Bit 15: event_fifo_full[0],

//Bit 14: event_desc_full[0],

//FATAL Errors*********************************************************

//Bit 13: idle_violation[0],

//Bit 12: busy_violation[0],

//Bit 11: fifo_read_overflow_reg[0],

//Bit 10: fifo_write_overflow_reg[0],

//Bit 9: pixel_fifo_full_reg[0],

//Bit 8: event_fifo_read_overflow[0],

//Bit 7: event_fifo_write_overflow[0],

//Bit 6: event_desc_full_violation[0],

//Bit 5: dpm_full[0],

//Bit 4: busy_out[0],

//Bit 3: fatal_error[0],

//Bit 2: event_desc_empty[0],

//Bit 1,0: 2'b0

};

assign busy_out[0] =

((busy_mcm[0] & busy_mask0[11]) | //default = 1

(event_fifo_full[0] & busy_mask0[10]) | //default = 1

(event_desc_full[0] & busy_mask0[9]) | //default = 1

fatal_error[0]) ;

assign fatal_error[0] =

(idle_violation[0] & busy_mask0[8]) | //default = 1

(busy_violation[0] & busy_mask0[7]) | //default = 1

(fifo_read_overflow_reg[0] & busy_mask0[6]) | //default = 1

(fifo_write_overflow_reg[0] & busy_mask0[5]) | //default = 1

(pixel_fifo_full_reg[0] & busy_mask0[4]) | //default = 1

(event_fifo_read_overflow[0] & busy_mask0[3]) | //default = 1

(event_fifo_write_overflow[0] & busy_mask0[2]) | //default = 1

(event_desc_full_violation[0] & busy_mask0[1]) | //default = 1

(dpm_full[0] & busy_mask0[0]); //default = 1

Status_bus has been removed Flag_latch removed


Rx Card Version 1224: event_desc_full flag is activated after 8 events instead of 2 after two. ev_fifo_full_violation flag published

Rx Card Version 1124://2008 05 13 busy_mask modified to exclude busy_mcm from busy_out -> only fatal errors are //forwarded on busy_out

Rx Card Version 1024: //AK 2008 04 25: added data_consistency_checker I added a data consistency check into the rxcard. The module will check whether the data written into the ram are correct with respect to the trailer, header, fill word and checks that the event counter only jump by 1.

state machine runs at 41 MHz

Rx Card Version 24: identical to V23 but: //L1_counter&L2_counter 8 bits count the number of received L1&L2 signals from the router //assign status3 [23:16] = l1_counter; //assign status3 [31:24] = l2_counter; //L1&L2 counters are added in input_stage_ver1 of both channels, but actually are needed //only in one-> the correct place should be rob.v saving 16 flipflops

the state machine runs at 39 MHz

Rx Card Version 23:

//MC&AK 20080416 L1_check_counter & L2_check_counter added in serialized status; //input_stage, status1[27:24] = l1_check_counter; status1[31:25] = l2_check_counter //these counters are 4'h7 in case the number of L1 sent to the rxcard equals the number of //L1 received as feedback signals from the detector. //The counter counts until 4'hf(4'h0) in case L1 are sent to the rxcard and not received //back by the MCM (are not sent to the rx card but feedback signals are active. Then the // freezes at the value 4'hf(4'h0). //Runs now at 41,14 MHz/75%

//AK 2008 04 11 removed pi_fifo_empty from the read_int command as in the data_encoder //the non_empty status is verified before a read command is issued //this removes a timing loop from data_encoder back to pixel_fifo and increases max frequency rob_ver1.v //AK 2008 04 09 reset_control_receiver removed as not used

//AK 2008 04 09 reset_pilot and reset_pilot_inverse commands inmplemented: //in order to reset the pilot chip //the router or directly from VME /// reset_pilot & reset_pilot_inverse // must be invoked each twice // 2 x reset_pilot and then 2 x reset_pilot_inverse

rx_control_ver3 //2008 04 07 after reset delay lines are programmed with 0 //AK 25.3.2008 added to reduce input to clock (setup) time of id, router_addr, r_ds_n, r_wr, router_data inserted registers for rst_n, d_ds, r_rw, router_addr, router_data in order to avoid setup time violations read delay of rx_card is increased by one clock cycle because of that.

Quartus results: V22 73% 36.01Mhz (34.45MHz with routing effort 3/4/Max) ##saved version## V21 81% 34.04Mhz V22 (input registers) 71% 34.99% V22 76% 36.79Mhz (mit global clock + analysisSynthesis setting optimization technique speed+ use netlist optimizations)

V23 74% 38.14 MHz ##saved version#


Rx Card Version 22: runs at 36 MHz, unused functionality removed.

rx_altera_1_core_ver2 schematic from cadence obselete. verilog file rx_altera_1_core_ver2.v is used located in verilog_altera; the same applies for link_channel_ver2.v

rx_control_ver3 0 //AK 2008 03 25 transparent mode + transserial removed + cntl[5:4] removed from status reg //change address output removed //L1 bus and memo counter removed + router counter removed+ enable_remove_bit //state_data_encoder_removed from status register

//AK 2008 03 25 templimit registers and entry in status register removed

data_encoder //2008 03 25 ak state_data ouput removed

rob_ver1.v://2008 03 25 ak mode transserial removed

histogramm functionality removed


Rx Card Version 21; builds up on version 17 (output registers have not been modified as in version 20) status registers of channel 1 have been copied from channel 0 and are now corrected.


Rx Card Version 20: not yet released; builds up on version 17, Version 18 and 19 do not work in real life. Reason unknown.

rx_control_ver3.v //AK 2008 01 11 inserted registers for rst_n, d_ds, r_rw, router_addr, router_data in order to avoid setup time violations read delay of rx_card is increased by one clock cycle because of that.


Rx Card Version 19: not yet released;

bit 23 in status register is 0 if all 10 chips are read out. it is 1 if 0 to 9 chips are read out.

the 10 bit maskchip register (defines which chips out of the 10 are read out) is sent from the rxcard to the router in the serialized status registers. in the field: chan0_status3_input_stage in bits 25 downto 16 with for chip 9 downto 0. (1 means chip is read out)

status_serializer a_status_serializer_chan0 ( .clk(clk40), .reset_i(reset_i), .status0(chan0_status0_input_stage), .status1(chan0_status1_input_stage), .status2(chan0_status2_input_stage), .status3(chan0_status3_input_stage), .status4(chan0_status_event_desc_ram), .status5(chan0_status_fifo_pixel_data), .status6(chan0_status_fifo_event_data), .status7(chan0_status0_data_encoder), .status8(chan0_status1_data_encoder), .status9(chan0_status2_data_encoder), .status10(chan0_status3_data_encoder), .status11(chan0_status4_data_encoder), .status12(chan0_status5_data_encoder), .status13(chan0_status6_data_encoder), .status14(chan0_status7_data_encoder), .status15(32'h15041968), //spare status bits .serial_out(chan0_serial_status), .parallel_load());

Rx Card Version 18: June 8, 2007;

//AK 2007 06 12 temperature limit removed, temperature exceed flag in status register removed

//AK 2007 06 12 cntl0/1 register shrinked to 6 bits, removed transparent mode (can be switched on againg by uncommenting the define variable enable_tranparent, removed serial_trans mode which allows the router to send data directly on the serial line ( can be switched on by uncommenting variable enable_serial_trans)

//AK 2007 06 08 shift_selector changed to fastormask, old shiftselector masked both channels identically, now fastormask exists for two channels, register is now only 10 bit wide bit 0 for chip 0, 0 deactivates corresponding fastOr output. Address is H33, channel bit switches between 0 and 1 channel

//AK 070612 time_cnt measures 100 ns cycles between FO and strobe, register address is h20, channelbit for switching between channels. Time is started if FastOr is received and stopped upon posedge strobe. If cnter is ff counting register is again set to 0. Counter is copied to readoutregister only upon posedge strobe.

//AK 2007 06 12 chan0/1_busy_out is latched and can only be set to 0 by reset_i or clear_data_i

________________________________

Rx Card Version 17: May 23, 2007; data_encoder_ver2: //May 23, 07 AK data_next_is_0 used to decode just one single remaining hit, this does not use minor and dec and is faster //May 23, 07 AK remaining_chips_next_is_0 used to decode just one single remaining hit, this does not use minor and dec and is faster

________________________________

Rx Card Version 16: Feb 23, 2007, rxerror_counter implemented, error_control_int_counter, rx_not_ready_counter implemented. all three counters count the number of clock cycles where the rxerror/error_control/rx_not_ready_counter is not 0/0/1. All three counters only start counting when the rx_ready was once 1. If link problems occor -> Check rxready_flag (must be '1') -> check rxerror_counter (if unequal 0 -> verify G-link -> check error_control_int counter (if unequal 0 -> verify clk, data) -> reset rx_card, repeat checking. Bob2003_fpga has been removed in order to gain logic cells, bob outputs l1, l2yl2n are taken from rob, jtag inputs to mcm_stimuli are directly taken from inputs to rob. mcm_stimuli_jtag: 256 cell delay line has been removed. Delay for fastor_shifted removed. Register delay is part of shift_selector has no function anymore (and should be removed from rx_control). Fastor_shifted and fastor_ored outputs/signals removed on schematic in rx_altera_1_core_ver2 as they were not used. On schematic rx_altera_1_core_ver2 option to switch clk on indication0/link_err0 deleted. Not used outputs on input_stage_ver1 removed. Status information sent to router (16 32-bit registers) only readable via router. No access on rx card directly. Status serializer uses 2 32 bit Fifos instead of 2 x 544 Flip Flops. 79% logic cell occupancy.

________________________________

Rx Card Version 15: Feb , 2007, status info serialized on jtag0/1_trst -> used as output to router.

________________________________

Rx Card Version 14: Jan 29, 2007 Status information forwarded from all blocks to rx_control_ver3

//AK 07 01 24 busy mask per default set to off, otherwise most errors will not be forwarded as busy to the router via indication bus

data_encoder_ver2.v://Jan 16, 2006 AK changed back as start_address is advanced too early for ram_address_pointer data_encoder_ver2.v://AK jan 9, 2007, included state_error; in case of dpm_full_int is active, the state is error_state is activated until reset. no registers or counters are advanced.

fifo_pixel_data_ver1.v://AK/GA jan 22 07; read_pointer/write_pointer reset changed from 8'b0 to 9'b0 fifo_pixel_data_ver1.v://AK/GA jan 22 07; fifo_read/write_overflow_reg is latched, can only be set to 0 by reset fifo_pixel_data_ver1.v://AK/GA jan 22 07; fifo_count set to zero in case fifo is read and fifo is empty. fifo_pixel_data_ver1.v://AK/GA jan 22 07; fifo_read/write_overflow_reg set using pi_fifo_write/pi_fifo_read as with pi_fifo_write_int the condition can never be fullfilled

input_stage_ver1.v://AK 070122 added status register

rx_control_ver3.v://AK 2007 01 25 inserted data delay in order to suppress the high amount of read_type rx_control_ver3.v://AK 07 01 24 busy mask per default switched, otherwise all errors will not be forwarded as busy to the router via indication bus

________________________________

Rx Card Version 13: Dec 18 , 2006 AK,

data_encoder_ver2.v //AK Dec15, 2006, write_event is independent of write_dpm, simulation shows that event length is not correct and can include 1 or possibly sereral full events, however event_length was pointing always to the end of an event; dpm_r_wen0_n removed from if clause events. If write_event is active but no new data is written to dpm event_length_counter ->0, otherwise -> 1

//as dpm_r_wen0_n is connected to the dpm cnt_enable signal dpm_r_wen0_n is used to incraese event_length_counter

//as dpm_r_wen0_n is connected to the dpm cnt_enable signal dpm_r_wen0_n is used to incraese ram_write_pointer

//Dec 14 06 AK ram_write deactivated in state wait for new line, removes double headers

//Dec 5, 2006, AK //ram_occupancy addded but not used yet.

________________________________

Rx Card Version 12: Dec 1 , 2006 AK, event_desc_ram_ver1.v //AK Nov 22, 2006, ram_count: if write_int and flush_int is active at the same time //ram_count decreases by three

________________________________

Nov 16. 2006, Progamming files and simulation files for rx cards are migrated to DSF. FPGA programming files are in folder: dsf.cern.ch/dsf/Services/cdsusers/akluge/cadence/spd/spd_rxcard/link_rx_card_2004_pascal/verilog_files/synth/Quartus_alex the programming files sof and pof have the name: rx_altera_1_core_ver1_v7.sof and rx_altera_1_core_ver1_v7.pof for version 7 as example

________________________________

Rx Card Version 11: Nov 16, 2006 start address bit 19 set to 0. DPM has only 19 bits address range. Router might get confused. Format checking added to router_data bus: copied from Marian's router. Detects missing header, trailer, output connected to LSA 8 -11, plus LED starts blinking upon error.

________________________________

Rx Card Version 10: August 28, 2006 After link is locked: rx_cntl must be active in slot 0,1 and inactive in 2,3; rx_data must be inactive in slot 0,1; otherwise signal error_format is active and error_format_cnt is incremented.

If number of transmitted half rows (betweeen first_word and last_word) is not 5120, error_data_trans is activated and error_data_trans (8 bit) is incremented.

Event number is checked; if it is increasing by more than 1; error_eventnumber_cnt is increased; error_eventnumber is activated. addded registers error_status_bus_a0 and _error_status_bus_a1 for the two channels of the rx card on register address d19.

assign error_status_bus [0] = error_format||error_data_trans||error_eventnumber; assign error_status_bus [1] = error_format; assign error_status_bus [2] = error_data_trans; assign error_status_bus [3] = error_eventnumber; assign error_status_bus [7:4] = 3'b0; assign error_status_bus [15:9] = error_format_cnt; assign error_status_bus [23:16] = error_data_trans_cnt; assign error_status_bus [31:24] = error_eventnumber_cnt;

-- Main.akluge - 28 Aug 2006

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