BGV Readout


Overview

  • Overview of readout & control


WATCH OUT: some new CTRL and DATA cables were made for the BGV. They look like the VELO cables, but there is a difference in the CTRL cables: these were made with the same type of cable as for the DATA!! (16 pairs instead of 17), see pin assigment documents: Cables pin-out for BGV: Pinning_cablage_DATA.pdf, Pinning_cablage_CONTROL.pdf

  • Photos of the VELO assembly lab and VELO Zap-test setup




  • New BGV interface RPT-Board to Beetles
    as proposed by EPFL / Raymond Frei (see in BGV meeting 3 feb 2014):
    rpt-Beetle-interface-3feb2014-raymond.png
    Modifications made to VELO RPT boards for use in BGV see here (in french, from raymond Frei):
    1. FE input resistors changed to adapt to different cable length to the Beetles,
    2. HV bias line modified,
    3. A wire is added between J25, J29 and the pins 27 et 29 of connector J14 to bring 3.3V to the LVDS drivers of the FERPT.
      The other modifications for interfacing to the BGV Beetles and SiPM are external to the RPT board. They are implemented in a "RPT fanout card" and "FE support card".
    • The RPT fanout card (also called "FERPT" or "FrontEnd Repeater card" or "FE_RPT Adaptor card") fans out the fast signals from the RPT board into four, to match the 4 Beetle FE boards.
    • The bias/guard/return connection on the RPT board (FE side) is disconnected, not used in the BGV. Bias voltage goes via the FE support card.
    • The VELO module temperature connector is also not used.
    • location of components for 60m data cable compensation: (view or save image to enlarge)

velo-driver-60mcable.png

LV, Bias and Temperature

Documentation (Raymond Frei)

CAEN Mainframe for LV and HV supply (Mariana Rihl)

  • for the power supply, the CAEN Mainframe 4527 is used (see manual here). It houses 5 LV supply cards and a "high voltage" supply card.
  • for the low voltage, the A2518 LV board is used. It has 8 channels, each with an output of up to 8 V or 10 A (50 W). The boards are individual floating channel boards.
    manual of the LV boards
  • to bias the SiPMs, the A1539 high voltage power supply is used. It has 32 individually settable channels. Each channel can have between 0 V and 100 V and a current of up to 10 mA. The board is a common floating return board.
    manual for the HV board.

TS2 & TS3 installation information

readout system information (Mariana Rihl)


  • BIAS
    • label of bias cable on downstream side was wrong. Cable 1425416 on service tunnel side was 1425417 on detector side. Exchanged cable on service tunnel side, so use 1425317 on CAEN mainframe and re-labelled on the detector side to *17.
    • these changes result in:
Board 11: upstream ch 0-15, cable 1425415
  downstream: ch 16-31, cable 1425417
  spare: cable 1425416

  • We realised there was a bug in the average breakdown voltage calculation for the 128-channels SiPMs (18.08.2016). The average values were therefore recalculated and the table below was updated. In the following excel sheet, you can find the breakdowns for each SiPM and calculated the bias voltages to apply for different over-voltage and temperatures: BGVmodule_VBDspreadsheet_updated.xls

Upstream:

Connector BIAS PATCH PANEL Sector Channel WinCC notation module bias Voltage
J1 S, R 0, 1 TOP QRL module 10-4L 57.34V, 58.36V
J2 U, T 2, 3 TOP QRL module 10-4L 57.66V, 57.55V
J3 S, R 4, 5 BOTTOM PASSAGE module 08-4L 57.96V, 57.42V
J4 U, T 6, 7 BOTTOM PASSAGE module 08-4L 58.14V, 57.63V
J5 S, R 8, 9 BOTTOM QRL module 07-4L 57.91V, 58.05V
J6 U, T 10, 11 BOTTOM QRL module 07-4L 57.38V, 57.72V
J7 S, R 12, 13 TOP PASSAGE module 09-4L 58.43V, 58.26V
J8 U, T 14, 15 TOP PASSAGE module 09-4L 58.38V, 58.39V

Downstream:

Connector BIAS PATCH PANEL Sector Channel WinCC notation module bias Voltage
J1 S, R 16, 17 TOP QRL module 01 58.30V, 58.05V
J2 U, T 18, 19 TOP QRL module 01 58.51V, 58.40V
J3 S, R 20, 21 BOTTOM PASSAGE module 02 57.90V, 57.95V
J4 U, T 22, 23 BOTTOM PASSAGE module 02 58.27V, 58.13V
J5 S, R 24, 25 BOTTOM QRL module 03 58.40V, 57.83V
J6 U, T 26, 27 BOTTOM QRL module 03 58.10V, 58.01V
J7 S, R 28, 29 TOP PASSAGE module 05 57.96V, 57.85V
J8 U, T 30, 31 TOP PASSAGE module 05 58.07V, 58.11V


  • CB Connectors
    • CB 22 (CB1 in PVSS, downstream): cable order with respect to CB ports
      * 1425423 is broken so:
      * 1425425 instead of 1425422 instead of 1425421 -> Bottom QRL
      * 1425422 instead of 1425425 instead of 1425422 -> Bottom Passage
      * 1425424 instead of 1425423 -> Top QRL
      * 1425421 instead of 1425424 -> Top Passage
    • CB 16 (CB0 in PVSS, upstream): cable order with respect to CB ports
      * 1425426 -> Bottom QRL
      * 1425427 -> Bottom Passage
      * 1425428 -> Top QRL
      * 1425429 -> Top Passage

  • Low Voltage
    • Board 01: Passage - upstream -> exchanged cable "UP_PAS_BOTTOM" with LV_Spare, because measured LV values on UP_PAS_BOTTOM were strange. Needs investigation (Cable? Patch Panel?).
    • Board 03: QRL - upstream -> ch5 always tripped -> had to put trip current to 2A instead of 1A, works now (11.11.2015).
    • Board 05: Passage - downstream
    • Board 07: QRL - downstream
    • these changes now result in:
board number location channels top channels bottom
Board01 upstream - Passage ch 0-2 Top ch 4-6 Bottom (LV_Spare)
Board03 upstream - QRL ch 0-2 Top ch 4-6 Bottom
Board05 downstream - Passage ch 0-2 Top ch 4-6 Bottom
Board07 downstream - QRL ch 0-2 Top ch 4-6 Bottom
Board09 Spare LV ch 0-2 (UP_PAS_BOTTOM)  

  • Temperature Readout
    • Unit 1: upstream
1404968 (TOP QRL) 1404970 (BOTTOM QRL, module 07-4L)
1404969 (BOTTOM PASS, module 08-4L) 1404971 (TOP PASS)
    • Unit 2: downstream
1404973 (TOP QRL) 1404975 (BOTTOM QRL, module 03-5L)
1404974 (BOTTOM PASS, module 02-5L) 1404976 (TOP PASS)

  • Data Readout - TELL1s
    • The data cables for the Tell1 go from the module to the service tunnel, where the rack with the Tell1s is installed.
      These 60m cables are divided in the following way:
      # 1425367 - 1425384 are reserved for the 4 downstream detector modules
      # 1425385 - 1425402 are reserved for the 4 upstream detector modules
      Spare Cables:
      .......................downstream: 1425383, 1425384
      ...................... upstream: 1425401, 1425302

    • all 8 detector modules are installed, the detector is complete.

up-/downstream bgvtell# module notation data- cable- number 1425***
        PPx0 PPx 1 PPX 2 PPx 3
up 09 10-4L TOP QRL 385 386 387 388
up 04 09-4L TOP Passage 389 390 391 392
up 06 08-4L BOTTOM Passage 393 394 395 396
up 05 07-4L BOTTOM QRL 397 398 399 400
down 01 01-5L TOP QRL 367 368 369 370
down 02 05-5L TOP Passage 371 372 373 374
down 07 02-5L BOTTOM Passage 375 376 377 378
down 08 03-5L BOTTOM QRL 379 380 381 382
            modules_id_arrangement_v3b.png


  • Summary - to be regularly updated

module Tell1 Software ID* LVBoard WinCC RPT WinCC Hybrid notation Control Board ControlBoard Cable Temperature Readout
07-4L bgvtell05 1 03 - ch 4-6 RPT04 CB0Hybrid0 upstream - Bottom QRL 16 1425426 1404970
08-4L bgvtell06 0 01 - ch 4-6 RPT02 CB0Hybrid1 upstream - Bottom Passage 16 1425427 1404969
10-4L bgvtell09 2 03 - ch 0-2 RPT03 CB0Hybrid2 upstream - Top QRL 16 1425428 1404968
09-4L bgvtell04 3 01 - ch 0-2 RPT01 CB0Hybrid3 upstream - Top Passage 16 1425429 1404971
                   
03-5L bgvtell08 5 07 - ch 4-6 RPT08 CB1Hybrid0 downstream - Bottom QRL 22 1425425 1404975
02-5L bgvtell07 4 05 - ch 4-6 RPT06 CB1Hybrid1 downstream - Bottom Passage 22 1425422 1404974
01-5L bgvtell01 6 07 - ch 4-6 RPT07 CB1Hybrid2 downstream - Top QRL 22 1425424 1404973
05-5L bgvtell02 7 05 - ch 4-6 RPT05 CB1Hybrid3 downstream - Top Passage 22 1425421 1404976

* as defined in the code:

Dead channels reported (Olivier Girard - preliminary tests at EPFL)

We report here the dead channels found on all modules tested at EPFL. More information about these tests: SciFiModulesAssemblyAndTestingEPFL. For the eight modules installed at the LHC, a total of 43 channels are dead which represents less than 0.3% of the total number of channels. Direct link to the excel table: Dead_channels_all_modules.xls

TELL1 ID Module name Module position PPX number FEBoard ID Beetle number Beetle ID Analog-link Channel (within analog-link) SiPM channel BGV channel
1 Modul1 Downstream-top-qrl 0 R 0 A 3 17 113 113
0 R 2 C 1 18 50 306
1 S 2 C 1 18 50 818
2 T 2 C 1 18 50 1330
3 U 2 C 1 18 50 1842
3 U 3 D 0 28 28 1948
7 Modul2 Downstream-bottom-passage 0 R 2 C 1 18 50 306
1 S 2 C 1 18 50 818
2 T 2 C 1 18 50 1330
3 U 2 C 1 18 50 1842
8 Modul03 Downstream-bottom-qrl 0 R 2 C 1 18 50 306
1 S 2 C 1 18 50 818
2 T 2 C 1 18 50 1330
3 U 2 C 1 18 50 1842
2 Modul05 Downstream-top-passage 0 R 2 C 1 18 50 306
1 S 2 C 1 18 50 818
2 T 2 C 1 18 50 1330
3 U 2 C 1 18 50 1842
Modul06-4L Spare module 0 R 1 B 1 28 60 188
0 R 1 B 3 20 116 244
0 R 2 C 1 18 50 306
1 S 2 C 1 18 50 818
2 T 2 C 1 18 50 1330
3 U 0 A 0 8 8 1544
3 U 2 C 1 18 50 1842
3 U 3 D 2 24 88 2008
5 Modul07-4L Upstream-bottom-qrl 0 R 2 C 1 18 50 306
1 S 2 C 1 18 50 818
2 T 1 B 1 25 57 1209
2 T 1 B 3 13 109 1261
2 T 2 C 1 18 50 1330
2 T 2 C 3 27 123 1403
2 T 3 D 1 17 49 1457
3 U 2 C 1 13 45 1837
3 U 2 C 1 18 50 1842
6 Modul08-4L Upstream-bottom-passage 0 R 0 A 2 24 88 88
0 R 0 A 3 8 104 104
0 R 2 C 1 18 50 306
1 S 0 A 0 2 2 514
1 S 2 C 1 18 50 818
2 T 2 C 1 18 50 1330
2 T 3 D 1 31 63 1471
3 U 2 C 1 18 50 1842
4 Modul09-4L Upstream-top-passage 0 R 2 C 1 18 50 306
1 S 2 C 1 18 50 818
2 T 2 C 1 18 50 1330
3 U 2 C 1 18 50 1842
9 Modul10-4L Upstream-top-qrl 0 R 2 C 1 18 50 306
1 S 2 C 1 18 50 818
2 T 2 C 1 18 50 1330
3 U 2 C 1 18 50 1842

Test pulses

The mask selecting which channel send a test pulse is "double inverted". Use the files /group/bgv/tpselect.py (in the online network) to create the correct mask corresponding to a given channel


CTRL Repeaters

Description

Installation photos


Documentation

Analysis

login to bgvctrl:

ssh -Y rootbgv@bgvgw

from there: ssh -Y rootbgv@bgvctrl

analysis files from EPFL: /group/bgv/CodeOlivier/

analysis scripts from Karol (has MCMS): /group/bgv/velo2-assembly.py

mdf files: /group/online/dataflow/data/Run_0000701_20150729-101138.bgvctrl.mdf

"Dark count" measurements (i.e. Bias On) are runs 701-704 (R, S, T, U), "pedestals" (i.e. Bias Off) are runs 683 (R), 686 (S), 689 (T), 678 (U)

To analyse mdf files:

  • source /cvmfs/lhcb.cern.ch/group_login.sh
  • SetupVetra
  • python /group/bgv/velo2-assembly.py /group/online/dataflow/data/Run_0000701_20150729-101138.bgvctrl.mdf (or other file name)

To analyse EPFL raw file:

  • source and Vetra again
  • cd /group/bgv/CodeOlivier
  • sh run_analysis.sh /group/online/dataflow/data/an_epfl_file_name

Note that this analysis code doesn't work on mdf files... the analysis is written for epfl raw files which have a different format than mdf files. Plots will be messed up.

To view contents of a binary file you can try the unix command "od", e.g. "od -t x4 -v d15ss.mdf | less" or "od -t x2 -v d15ss.raw | less", shows data in 4hex-by-4hex format.

To analyse PULSESHAPESCAN:

  • source and Vetra
  • LbLogin -c x86_64-slc6-gcc48-opt
  • SetupVetra v15r0
  • cd /home/mrihl/cmtuser/Vetra_v15r0/Tell1/Vetra/cmt
  • make
  • cd ../options/Velo
  • vi Vetra-pulseshapeplotter_MR.py
  • change lines 90 and ongoing for mdf (input) file names
  • change line 112 for output file name (and path if necessary)
  • gaudirun.py Vetra-pulseshapeplotter_MR.py

  • if changes are needed in the analysis, the file is PulseShapePlotter.cpp and can be found under /home/mrihl/cmtuser/Vetra_v15r0/Velo/VeloDataMonitor/src/ . From /home/mrihl/cmtuser/Vetra_v15r0/Velo do 'make' to compile code again.

Raw data treatment and correction

RawDataTreatmentCorrection

Topic attachments
I Attachment History Action Size Date Who Comment
PDFpdf A1540_rev2.pdf r1 manage 900.6 K 2015-09-21 - 12:03 MarianaRihl  
PDFpdf A2518_rev2.pdf r1 manage 1095.3 K 2015-09-21 - 12:03 MarianaRihl  
Compressed Zip archivezip BGV_INST_bias.zip r1 manage 496.4 K 2015-09-01 - 20:33 PlamenHopchev  
Compressed Zip archivezip BGV_INST_low_voltage.zip r1 manage 1134.2 K 2015-09-01 - 20:33 PlamenHopchev  
Compressed Zip archivezip BGV_INST_temp.zip r1 manage 270.5 K 2015-09-01 - 20:33 PlamenHopchev  
Microsoft Excel Spreadsheetxls BGVmodule_VBDspreadsheet_updated.xls r1 manage 38.5 K 2016-08-19 - 10:45 OlivierGoranGirard  
Microsoft Excel Spreadsheetxls Dead_channels_all_modules.xls r1 manage 19.0 K 2015-12-16 - 14:07 OlivierGoranGirard  
JPEGjpg IMG_9177.JPG r1 manage 2953.8 K 2015-06-18 - 22:46 PlamenHopchev CTRL_RPT_Photos
JPEGjpg IMG_9180.JPG r1 manage 2431.5 K 2015-06-18 - 22:46 PlamenHopchev CTRL_RPT_Photos
JPEGjpg IMG_9224.JPG r1 manage 2559.0 K 2015-06-19 - 14:47 PlamenHopchev CTRL_RPT_Photos
JPEGjpg IMG_9225.JPG r1 manage 2740.5 K 2015-06-19 - 14:45 PlamenHopchev CTRL_RPT_Photos
PDFpdf Modifications_VELO_RPT_board_pour_BGV.pdf r1 manage 11.5 K 2014-07-25 - 11:38 MassiFL Modifications of RPT board for BGV (in french)
PDFpdf Pinning_cablage_CONTROL.pdf r1 manage 72.5 K 2014-02-03 - 12:24 MassiFL Pin-out CTRL cables for BGV
PDFpdf Pinning_cablage_DATA.pdf r1 manage 67.9 K 2014-02-03 - 12:23 MassiFL Pin-out DATA cables for BGV
PDFpdf SY4527_rev12.pdf r1 manage 2215.0 K 2015-09-21 - 12:03 MarianaRihl  
PNGpng VELO_Zap_FE_Board.png r1 manage 710.1 K 2014-03-25 - 10:58 PlamenHopchev  
PNGpng VELO_Zap_Readout_Sytem_Rack.png r1 manage 613.5 K 2014-03-25 - 10:58 PlamenHopchev  
PDFpdf guido_haefeli_fr_25.1.2008_tutorial_cmd_line_tool.pdf r1 manage 708.0 K 2014-01-14 - 17:11 MassiFL Guido's 2008 TELL+ tutorial in PDF
PNGpng readout-and-control-overview-v2.png r1 manage 37.2 K 2013-12-16 - 12:44 MassiFL readout-and-control-overview-v2
PNGpng readout-and-control-overview.png r1 manage 44.4 K 2013-08-12 - 16:06 MassiFL Overview of readout & control
PNGpng readout-and-control-overview_v3.png r2 r1 manage 38.8 K 2014-02-03 - 14:16 MassiFL readout-and-control-overview-v3
PNGpng readout-and-control-overview_v4.png r3 r2 r1 manage 14.9 K 2015-11-04 - 16:24 MassiFL readout-and-control-overview-v4
PNGpng rpt-Beetle-interface-3feb2014-raymond.png r1 manage 37.5 K 2014-07-25 - 09:12 MassiFL New BGV interface RPT to Beetle from EPFL / Raymond Frei
PNGpng velo-driver-60mcable.png r1 manage 126.4 K 2015-07-31 - 08:36 MassiFL location of components for 60m data cable compensation
Edit | Attach | Watch | Print version | History: r46 < r45 < r44 < r43 < r42 | Backlinks | Raw View | WYSIWYG | More topic actions
Topic revision: r46 - 2016-10-03 - BenediktWurkner
 
    • Cern Search Icon Cern Search
    • TWiki Search Icon TWiki Search
    • Google Search Icon Google Search

    BGV All webs login

This site is powered by the TWiki collaboration platform Powered by PerlCopyright & 2008-2021 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
or Ideas, requests, problems regarding TWiki? use Discourse or Send feedback