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Diamond Detector Secondary Shower Acquisiton System

ICECAL_V3 Mezzanine > ICECAL_V3 and AD41240 Readout: Total Linearity and Noise

1. Test Set-up

The linearity measurements are done with short pulses, and the input stages of the ICECAL are AC coupled, therefore these input signals must be synchronized with respect to the ICECAL integrators and ADC aqquisition clock. One of the channels of a Tektronix AFG3252 is used to provide test pulses (negative) to the ICECAL input whereas the second one is used as a system clock (emulating the 40MHz LHC Clock) for syncronization. The system clock is propagated through the optical link, allowing the front-end to be in synchronization with this clock. The test pulses are generated at 40KHz, in syncronization with the 40MHz clock, and therefore the ICECAL Front-End, which ensures that the test pulses will have no phase drift with respect to the acquisition electronics. The following figures show the test set-up and the related parts of the board tested.

Figure 1. Test Set-up with main components detailed and ICECAL_V3 Board with parts characterized for this tests highlighted.

2. Total System Noise Distribution with ICECAL and AD41240 Readout

The noise distribution of the whole readout assembly has been measured by loading all the ICECAL Inputs with 50 ohms. The ICECAL inputs, as well as its connection with the THS4521 ADC drivers are AC coupled with 100nF capacitors for safety. Each of the ICECAL Subchannels has been treated separatelly for noise calculations due to the different offset value observed (this offset can be compensated with the internal registers configurations, but it's very complicated to have both subchannels perfectly overlapped). A temporal window of 2.5ms has been taken for noise measurements (1.000.000 Samples @ 40MSPS), and a histogram on the raw ADC Data is performed to obtain the noise distribution and a gaussian fit performed to extract noise sigma value.

The figure bellow shows that the noise sigma for all channels and subchannels remains bellow 1.7 ADC Counts, this value is known to vary when the F.Generator is introduced on the readout chain up to 2-3ADC counts (Generator noise).

Fibure 2. Noise distributions for the four ICECAL channels, each subchannel is studied independently (first two rows), and raw ADC data (bottom row).

3. Total System Linearity with ICECAL and AD41240 Readout

The linearity measurements have been done with a sweep on amplitude of short negative pulses. The test pulses width is 50ns with a repetition frequency of 40Khz, this configuration allows that two consecutive acquisitions (25ns) are performed each 1000 samples (25us). Since consecutive acquisitions are performed with different subchannels, one sweep per channel is enough to characterize both subchannels. The pulses amplitude sweep is performed between 50mv-800mV, and a 30dB attenuator is placed just after the function generator, the charge sweep per 25ns windows seen by the ICECAL is therefore 790fC-12.6pC. Previous to the measurements, the ICECAL delay lines have been adjusted to match the 50ns pulses phase into two consecutive acquisitons (Phase_TH from the delay line channel control register), also the integrator capacitors tuned to reach a similar gain in all channels (CINT from ICECAL Channel Control register).

The figure bellow shows that the tuning of the integrator capacitor allow us to reach a similar slope (except on CH4 where a better tuning could have been reached). The typical slope for each of the ICECAL channels together with the ADC and drivers shows 1.6e14 ADC count/C, which is translated into approximatelly 6.25fC/ADC Count. Considering a noise level with sigma ~ 2ADC counts, this set-up as it is would roughly allow the identification of 25fC pulses with saturation around 12pC (500 Dynamic range per channel).

Figure 3. Linearity test results for the four ICECAL Channels (top) and residual non linearity (bottom). Each subchannel is studied independently. Here the version with Absolute Errors in ADC counts.