CALICE CLOCK AND CONTROL CARD - CCC - MANUAL

Draft 1.0

Martin Postranecky, Matthew Warren - UCL, 08 APRIL 2009

The CALICE "Clock & Control Card" - "CCC" - has been designed to
provide a clock and control/data fanout to ODRs or LDAs or stand-alone
DIFs, and to provide feedback/busy 'OR' from DIFs/LDAs for run control.
It can also provide stand-alone clock, and clock and control/data
fanout from other external sources.

* see DIAGRAM-1 : OVERALL CALICE DAQ ARCHITECTURE
  http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_CALICE-DAQ_Diag-1.ppt

It has a separate fast-signalling ( asynchronous ) line for low
latency pulse transfer.

It is designed to connect to LDAs/DIFs and ODRs using the 'standard' 
HDMI connectors and cables as used by CLink ( see schem.08 & 09 )

* see DIAGRAM-2 : HDMI SIGNALS
  http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_HDMI-SIGNALS_Diag-2.ppt


HARDWARE OVERVIEW :
-------------------

* see DIAGRAM-3 : CCC PHOTO
  http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_PHOTO_Diag-3.ppt

* see CIRCUIT DIAGRAMS :
  http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_pc3405m-Schematics.pdf

* see PCB LAYOUT and LINKS :
  http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_pc3405m1_Top-Silk.pdf


The CCC description can conveniently be split into six separate 
sections according to their functionality :

* see DIAGRAM-4 : CCC BLOCK DIAGRAM
  http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_BLOCK-DIAGRAM_Diag-4.ppt

1) CLOCK fanout ( including stand-alone clock generation )
   ( see schem.01 & 02 )

2) FAST Low Latency ( asynchronous ) pulse fanout ( see schem.03 )

3) CONTROL / DATA selection and fanout ( see schem.04 )

4) GENERAL ( BUSY ) 'OR' and feedback ( see schem.05 )

5) SPARE  / DATA 'OR' and feedback ( see schem.07 )

6) Combined functionality of above 1-5 using an on-board CPLD
   and/or an Expansion / Test / Debug Header ( see schem.06 )

NOTE : SECTIONS 1-5 ARE PURELY HARDWARE SELECTABLE, AND USE LINKS
------ TO SELECT VARIOUS OPTIONS.

Section 6 is capable of being software controlled via RS232 link
to the CPLD and/or by using pre-programmed setups on the CPLD.
The CPLD firmware can be modified or customised as required.


HARDWARE DESCRIPTION :
----------------------

NOTES:  - DEFAULT SETTINGS indicated by '#'
------  - SETTINGS for STAND-ALONE TESTING indicated by '*'
        - NIM : -ve standard, terminated 50R, DC-coupled,
                             ( unless otherwise described )

* see DIAGRAM-5 : ANNOTATED LAYOUT
  http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_ANNOTATED-LAYOUT_Diag-5.ppt


1A) CLOCK INPUTS ( see schem.01 )
=================================

There are THREE separate external CLOCK input connectors :
1x LVDS differential pair, 1x LVTTL and 1x NIM / TTL.

ONLY ONE of these three inputs should be used at any one time.

The external clock can be at any frequency between 50 - 150MHz
and must be CONTINUOUS.

If the external clock stops for 3 pulses, the on-board MPX/PLL
will switch to the stand-alone X-tal 50MHz clock. The transition
will be smooth and glitch-free, and can last up to 200 usec depending
on the frequency difference.

When the external clock re-starts, the MPX/PLL will switch back to
this external clock ( with SW2 in the AUTO position ).

INPUTS :
    a) LVDS differential pair, 100R terminated, DC-coupled :
       -----------------------------------------------------
       SMA-1A = SK18 :  LCLK1IN+  -> U45/2
       SMA-1B = SK28 :  LCLK1IN-  -> U45/1

( Alternatively, OPTIONAL CLOCK INPUT on HDMI-9 could be used :

    b) LVDS differential pair, 100R terminated, AC-coupled
       ---------------------------------------------------
       HDMI-9 = SK29 / pin 1 : LCLK2IN+ -> U45/2
       HDMI-9 = SK29 / pin 3 : LCLK2IN- -> U45/1

NOTE : Using the HDMI-9 inputs require adding and removing
------ smd components and is not trivial.
       
       FOR DETAILS, see circuit diagram on schem.03 and consult
       UCL before use   )

    c) TTL / LVTTL single-ended input :
       --------------------------------
       NIM-2 = SK33/2 : TCLKIN  ->   U40/2
 
    d) NIM / TTL / LVTTL single-ended input :
       --------------------------------------
       NIM-1 = SK33/1 : NCLKIN  -> link LK25

               LK25/1+2 #     = TTL
                    LK25/1+3 & 2+4 = NIM 

                    ( for AC-coupling remove R140 )

    NOTE : ONLY ONE of the three external inputs a) or b),c),d) should be
    ------ active at any one time !

    e) Internal stand-alone 50MHz clock : 
       ----------------------------------

       - to select stand-alone clock, slide SW2/1 to A = XTAL
       - to select any external clock a),b),c),d), slide SW2/1 to 1 = AUTO

         NOTE : In this position, the clock MPX/PLL U31 will automatically
         ------ revert to the internal stand-alone clock if no external
                clock is present for more than 3 pulses.

      If this happens, the output clock will drift slowly to
                the 50MHz stand-alone frequency. The transition will
      be smooth and glitch-free, and can last up to 200 usec
                depending on the frequency difference.

      When the external clock re-starts, the MPX/PLL will
      switch back to this external clock.


       LED INDICATORS : - DS1 yellow LED indicates an external clock
       ----------------   is present

                        - DS2 red LED indicates the internal stand-alone
           clock is selected by SW2


    f) TTL / LVTTL direct single-ended external input :
       ------------------------------------------------
       NIM-3 = SK34/1 : ECLKTIN -> LK15/3 & LK16/3

         by-passes the clock MPX/PLL U31 ( see 1B below )

1B) CLOCK OUTPUTS ( see schem.02 )
==================================

There are THREE sets of LVDS differential pair output connectors :
8x on HDMI, 8x on 10x2 DIL Header, 2x on SMA pairs

There are also 2x single-ended LVTTL and 2x NIM output connectors
on LEMO 00 ( 'NIM' ) connectors.

       link LK15/1+2 # = enables any selected clock a),b),c),d),e)
                         to clock output sockets
            LK15/2+3   = enables an external, non-PLL-ed clock from
          socket NIM-3 = SK34/1 ( see 1A/e above )
                         to the clock output sockets

       link LK16/1+2 # = enables any selected clock a),b),c),d),e)
                         to CPLD clock and on Expansion Header PL4/49
            LK16/2+3   = enables an external, non-PLL-ed clock from
          socket NIM-3 = SK34/1 ( see 1A/e above )
                         to CPLD clock and on Expansion Header PL4/49

OUTPUTS :
    a) 8+8+2 LVDS differential pairs, DC-coupled :
       -------------------------------------------
       HDMI<1-8> = SK<1-8> / pin 1 : LCLK<1-8>OUT+ from U12
            / pin 3 : LCLK<1-8>OUT- from U12

                 link LK5/1+2 # = insert to enable
                        U12 outputs

       DIL HEADER H-1 = PL6 / pins A1+B1  : GND
             / pins A<2-9> : LCLK<11-18>OUT+ from U35
             / pins B<2-9> : LCLK<11-18>OUT- from U35
             / pins A10+B10: GND

       SMA-19A = SK17 : LCLK19OUT+ from U35/13
       SMA-19B = SK27 : LCLK19OUT- from U35/14

       SMA-20A = SK16 : LCLK20OUT+ from U35/11
       SMA-20B = SK26 : LCLK20OUT- from U35/12

         link LK19/1+2 # = insert to enable
                 U35 outputs

    b) 2x LVTTL single-ended :
       -----------------------
       NIM-4 = SK35/1 : TCLK1OUT from U28
       NIM-5 = SK35/2 : TCLK2OUT from U28

    c) 2x NIM single-ended :
       ---------------------
       NIM-6 = SK36/1 : NCLK2OUT from U48
       NIM-7 = SK36/2 : NCLK1OUT from U48

       To select POLARITY of these NIM outputs, use link LK23 & LK22 :

         Link LK23/1+2   = NCLK2OUT = inverted
              LK23/2+3 # = NCLK2OUT = true
                       ( NIM -ve standard )

         Link LK22/1+2   = NCLK1OUT = inverted
              LK22/2+3 # = NCLK1OUT = true
                       ( NIM -ve standard )

2A) FAST Low Latency ( asynchronous ) pulse INPUTS ( see schem.03 )
===================================================================

There are TWO separate external FAST input connectors :
1x LVDS and 1x ECL differential pairs.

There is additional LVDS input from the Expansion Header, and
separate LVTTL inputs from the Expansion Header and from on-board CPLD.

ONLY ONE of these five external inputs below should be selected at any
one time by the links LK17 & LK18.

INPUTS :
    a) LVDS differential pair, 100R terminated, DC-coupled :
       -----------------------------------------------------
       SMA-2A = SK15 : LFTRIG1IN+ -> U44/3+U34/3+U25/2+3
       SMA-2B = SK25 : LFTRIG1IN- -> U44/2+U34/2+U25/1+4

    b) LVDS differential pair, 100R terminated, DC-coupled
       ---------------------------------------------------
       from the Expansion Header :
       ---------------------------
       PL4/3 : LFTRIGINP+ -> U24/3
       PL4/4 : LFTRIGINP- -> U24/2

( Alternatively, OPTIONAL CLOCK INPUT on HDMI-9 could be used :

    c) LVDS differential pair, 100R terminated, AC-coupled
       ---------------------------------------------------
       HDMI-9 = SK29 / pin 15 : LFTRIG2IN+ -> U44/3+U34/3+U25/2+3
       HDMI-9 = SK29 / pin 16 : LFTRIG2IN- -> U44/2+U34/2+U25/1+4

NOTE : Using the HDMI-9 inputs require adding and removing
------ smd components and is not trivial.
       
       FOR DETAILS, see circuit diagram on schem.03 and consult
       UCL before use   )

    d) ECL differential pair, AC-coupled, terminated :
       -----------------------------------------------
       2-pin LEMO = SK32/B2 : EFTRIG3IN+ -> U43/3
          SK32/A1 : EFTRIG3IN- -> U43/2

    e) LVTTL from the Expansion Header :
       ---------------------------------
       PL4/11 : LFTRIGTINP -> U33/2

    f) LVTTL from the on-board CPLD U9 :
       ---------------------------------
       U9/142 :   LFTRIGTINC -> U33/3

    NOTE : ONLY ONE of the six inputs a),b),c),d),e),f) above should
    ------ be selected at any one time !


2B) FAST Low Latency ( asynchronous ) pulse OUTPUTS ( see schem.03 )
====================================================================

    To select ONE ONLY of the above a)-f) inputs to pass to the
    output sockets, insert shorting link on the appropriate pins
    of links LK17(+) and LK18(-):

       LK17/1A+B & LK18/1A+1B # = LVDS input from SMA-2A+B sockets a)
                                  or from HDMI-9 c)
       LK17/2A+B & LK18/2A+1B   = LVDS input from Expansion Header b)
       LK17/3A+B & LK18/3A+1B   = LVTTL input from Expansion Header e)
       LK17/4A+B & LK18/4A+1B * = LVTTL input from the on-board CPLD U9 f)
       LK17/5A+B & LK18/5A+1B   = ECL input from SK32 d) 

OUTPUT :
    a) 8x LVDS differential pairs, DC-coupled :
       ----------------------------------------
       HDMI<1-8> = SK<1-8> / pin 15 : LFTRIG<1-8>OUT+ from U11
            / pin 16 : LFTRIG<1-8>OUT- from U11

                 link LK4/1+2 # = insert to enable
                        U11 outputs


3A) CONTROL / DATA INPUTS ( see schem.04 )
==========================================

There are FOUR separate sets of CONTROL / DATA input connectors :
4x LVDS differential pairs and 4x NIM / TTL.

Additionally, there are separate LVTTL inputs from the Expansion
Header and from the on-board CPLD.

ANY NUMBER of the inputs below can be selected by link LK12.
They will be "OR-ed" to provide a single output ( ie. NOTE POLARITY )

NOTE : All CONTROL / DATA are assumed to be LOW=ASSERTED logic.
------ Use links LK13, LK14, LK20, LK21 to change polarity as required.

INPUTS :
    a) 4x LVDS differential pair, 100R terminated, DC-coupled :
       -------------------------------------------------------
       SMA-<3-6>A = SK<14-11> : LCONT<1-4>IN+ -> U39
       SMA-<3-6>B = SK<24-21> : LCONT<1-4>IN- -> U39

( Alternatively, OPTIONAL CLOCK INPUT on HDMI-9 could be used :

    b) LVDS differential pair, 100R terminated, AC-coupled
       ---------------------------------------------------
       HDMI-9 = SK29 / pin 4 : LCONT5IN+ -> U39/2
       HDMI-9 = SK29 / pin 6 : LCONT5IN- -> U39/1

NOTE : Using the HDMI-9 inputs require adding and removing
------ smd components and is not trivial.
       
       FOR DETAILS, see circuit diagram on schem.03 and consult
       UCL before use   )

    c) 4x NIM / TTL / LVTTL single-ended inputs :
       ------------------------------------------
       NIM-<8-11> = SK<37-38>/1+2 : NCONT<1-4>IN  -> link LK<29-32>

                LK<29-32>/1+2 #     = TTL
                LK<29-32>/1+3 & 2+4 = NIM 

                ( for AC-coupling remove
                  R155, R159, R163, R167 )

       To select POLARITY of these four CONT<1-4>IN signals ( when
       converted to internal LVTTL level ) use links LK<13-14,20-21> :

                     LK<13-14,20-21>/1+2 * = inverted
                LK<13-14,20-21>/2+3   = non-inverted

    d) LVTTL from the Expansion Header :
       --------------------------------
       PL4/15 : CONTTINP -> U30/4

    e) LVTTL from the on-board CPLD U9 :
       ---------------------------------
       U9/74 :   CONTTINC -> LK12/6A

3B) CONTROL / DATA OUTPUTS ( see schem.04 )
===========================================

To select ONE ( or more ) of the above a)-e) inputs to pass to the
output sockets, insert shorting links on the appropriate pins
of link LK12 :

       LK12/1A+1B   = LVDS input from SMA-3A+B sockets a),
            or TTL / NIM inputs from NIM-8 socket c),
                      or LVDS input from HDMI-9 b)
       LK12/2A+2B   = LVDS input from SMA-4A+B sockets a),
            or TTL / NIM inputs from NIM-9 socket c)
       LK12/3A+3B   = LVDS input from SMA-5A+B sockets a),
            or TTL / NIM inputs from NIM-10 socket c)
       LK12/4A+4B   = LVDS input from SMA-6A+B sockets a),
            or TTL / NIM inputs from NIM-11 socket c)
       LK12/5A+5B   = LVTTL input from the Expansion Header d)
       LK12/6A+6B * = LVTTL input from the on-board CPLD U9 e)

An overall "OR" of the selected inputs is connected to the outputs.
( ie. NOTE POLARITY of selected inputs )

OUTPUTS :         
    a) 8x LVDS differential pairs, DC-coupled :
       ----------------------------------------
       HDMI<1-8> = SK<1-8> / pin 4 : LCONT<1-8>OUT+ from U18
            / pin 6 : LCONT<1-8>OUT- from U18

                 link LK6/1+2 # = insert to enable
                        U18 outputs

    b) LVTTL single-ended :
       --------------------
       NIM-15 = SK39/1 : TCONTOUT from U28


4A) GENERAL ( BUSY ) INPUTS ( see schem.05 )
============================================

There are EIGHT separate GENERAL / BUSY input connectors :
8x LVDS differential pairs.

These eights lines are "OR-ed" on board to provide a single
input line.

In addition, there are separate LVTTL inputs from the Expansion
Header and from the on-board CPLD.

ONLY ONE of these three input lines below should be selected at
any one time by the link LK3.

INPUTS :
    a) 8x LVDS differential pairs, 100R terminated, AC-coupled :
       ---------------------------------------------------------
       HDMI<1-8> = SK<1-8> / pin 7 : LBUSY<1-8>IN+ -> U2 + U4
            / pin 9 : LBUSY<1-8>IN- -> U2 + U4
 

    b) LVTTL from the Expansion Header :
       ---------------------------------
       PL4/17 : BUSYTINP -> U13/2

    c) LVTTL from the on-board CPLD U9 :
       ---------------------------------
       U9/40 :   BUSYTINC -> LK3/3A

    NOTE : ONLY ONE of the three inputs a),b),c) should be
    ------ selected at any one time !


4B) GENERAL ( BUSY ) OUTPUTS ( see schem.05 )
=============================================

    To select ONE of above three a)-c) inputs to pass to the
    output sockets, insert shorting link on the appropriate
    pins of link LK3 :

       LK3/1A+1B # =  Overall 'OR' of 8x LVDS inputs from 
            HDMI<1-8> = SK<1-8> sockets a)
       LK3/2A+2B   =  LVTTL input from the Expansion Header b)
       LK3/3A+3B * =  LVTTL input from the on-board CPLD U9 c)

       * USE FOR STAND-ALONE TESTING 


OUTPUTS :
    a) LVDS differential pair, DC-coupled :
       ------------------------------------
       SMA-8A = SK10 : LBUSY1OUT+ from U38/7
       SMA-8B = SK20 : LBUSY1OUT- from U38/8

    b) LVDS differential pair, 100R terminated, DC-coupled :
       -----------------------------------------------------
       HDMI-9 = SK29 / pin 7 : LBUSY2OUT+ from U38/6
       HDMI-9 = SK29 / pin 9 : LBUSY2OUT- from U38/5
       
    c) LVTTL single-ended :
       --------------------
       NIM-16 = SK39/2 : TBUSYOUT from U13/4

    d) TTL open-collector :
       --------------------
       NIM-12 = SK40/1 : OCBUSYOUT from LK24/2

       To select POLARITY of this TTL O/C output, use link LK24 :

          LK24/1+2 # = inverted
          LK24/2+3   = non-inverted

    c) NIM single-ended :
       ------------------
       NIM-13 = SK40/2 : NBUSYOUT from U51/4

       To select POLARITY of this NIM output, use link LK27 :

         Link LK27/1+2   = NBUSYOUT = inverted
              LK27/2+3 # = NBUSYOUT = true
                       ( NIM -ve standard )



5A) SPARE  / DATA INPUTS ( see schem.07 )
=========================================

There are EIGHT separate SPARE / DATA input connectors :
8x LVDS differential pairs.

There is no dedicated hardware handling these inputs, but
they are sent directly to the Expansion Header and to the 
on-board CPLD as LVTTL signals.

In addition, there are separate LVTTL inputs from the Expansion
Header and from the on-board CPLD. ONLY ONE of these two input
lines should be selected at any one time by the link LK7.

INPUTS :
    a) 8x LVDS differential pairs, 100R terminated, AC-coupled :
       ---------------------------------------------------------
       HDMI<1-8> = SK<1-8> / pin 10 : LSPARE<1-8>IN+ -> U5 + U7
            / pin 12 : LSPARE<1-8>IN- -> U5 + U7
 
    NOTE : These inputs above are NOT HARDWARE SELECTABLE by links
    ------

    b) LVTTL from the Expansion Header :
       --------------------------------
       PL4/19 : SPARETINP -> U13/11

    c) LVTTL from the on-board CPLD U9 :
       ---------------------------------
       U9/41 :   SPARETINC -> LK7/1B

    NOTE : ONLY ONE of these two inputs b),c) above should be selected
    ------ at any one time !



5B) SPARE  / DATA OUTPUTS ( see schem.07 )
==========================================

    To select ONE of the above two b), c) inputs to pass to the
    output sockets, insert shorting link on the appropriate pins
    of link LK7 :

       LK7/1A+2A   =  LVTTL input from the Expansion Header b)
       LK7/1B+2B # =  LVTTL input from the on-board CPLD U9 c)

    NOTE : THE LABEL OF THIS LINK LK7 IS INCORRECT ON PCB
    -----------------------------------------------------

OUTPUTS :
    a) LVDS differential pair, DC-coupled :
       ------------------------------------
       SMA-11A = SK9  : LSPARE1OUT+ from U20/6
       SMA-11B = SK19 : LSPARE1OUT- from U20/5

    b) LVDS differential pair, 100R terminated, DC-coupled
       ---------------------------------------------------
       HDMI-9 = SK29 / pin 10 : LSPARE2OUT+ from U20/7
       HDMI-9 = SK29 / pin 12 : LSPARE2OUT- from U20/8

    c) LVTTL single-ended :
       --------------------
       NIM-14 = SK34/2 : TSPAREOUT from U13/7



6) Combined functionality of above 1-5 using the on-board CPLD
==============================================================
   and/or the Expansion / Test / Debug Header ( see schem.06 )
   ===========================================================
 
All the various input signals from sections 1-5 are made available
on the Expansion Header PL4, and also connected to input pins of
the on-board CPLD U9 :


1) CLOCK INPUTS :
-----------------
    a) LVTTL to the Expansion Header :
       -------------------------------
       PL4/49 : MCLKTOUTP from U27/6

    b) LVTTL to the on-board CPLD U9 :
       -------------------------------
       DL1/6 :  MCLKTOUTC from U27/6

NOTE : The onboard CPLD U9 has four separate clock input pins 
------ INCLK<0-3>.

       The clock INCLK3 on U9/125 is connected to the MCLKTOUTC
       via a delay line DL1. This enables this clock to be delayed
       in 64 steps of 0.5nsec, thus allowing for changes in phase
       between the selected output clock and the processed signal
       outputs from the CPLD.


2) FAST INPUTS :
----------------
    a) LVDS differential pair to the Expansion Header :
       ------------------------------------------------
       PL4/7 :  LFTRIGOUTP+ from U34/6
       PL4/8 :  LFTRIGOUTP- from U34/7

    b) LVTTL to the Expansion Header :
       -------------------------------
       PL4/13 : LFTRIGTOUTP from U25/7

    c) LVTTL to the on-board CPLD U9 :
       ------------------------------- 
       U9/143 : LFTRIGTOUTC from U25/6


3) CONTROL / DATA INPUTS :
--------------------------
    a) 4x LVTTL to the Expansion Header :
       ----------------------------------
       PL4/12,14,16,18 : MCONT<1-4>TOUTP from U30<11-14>

    b) 4x LVTTL to the on-board CPLD U9 :
       ----------------------------------
       U9/<77-80> :  MCONT<1-4>T from U29


4) GENERAL ( BUSY ) INPUTS :
----------------------------
    a) 8x LVTTL to the Expansion Header :
       ----------------------------------
       PL4/20,22,24,26,28,30,32,34 : LBUSY<1-8>TOUTP from U6 & U8

    b) 8x LVTTL to the on-board CPLD U9 :
       ----------------------------------
       U9/<1,2,5-10> : LBUSY<1-9>T from U6 & U8


5) SPARE / DATA INPUTS :
------------------------
    a) 8x LVTTL to the Expansion Header :
       ----------------------------------
       PL4/36,38,40,42,44,46,48,50 : LSPARE<1-8>TOUTP from U5 & U7

    b) 8x LVTTL to the on-board CPLD U9 :
       ----------------------------------
       U9/<18,21-28> : LSPARE<1-9>T from U5 & U7


Thus, all above signals can be processed as required by on-board CPLD
and/or externally via the Expansion Header, and relevant outputs then
fed back to the CCC ( as inputs described in sections 1-5 ).

The CPLD is capable of being software controlled via RS232 link
using D9 connector = SK31 ( see schem.07 ) and/or by using
pre-programmed firmware sections on the CPLD.

There is also a HEX rotary switch selector connected to the
CPLD which can be used for testing or to select a pre-programmed
sections of the firmware.

The CPLD firmware can be modified or customised as required using
JTAG connectors J1 or J2 ( see schem.06 ). 

NOTE : To isolate the JTAG connections to CPLD U9, remove these
------ four links :
         LK8  = TDI
         LK9  = TDO
         LK10 = TMS
         LK11 = TCK


7) ADDITIONAL HARDWARE INFORMATION
==================================


a) POWER SUPPLY REQUIREMENTS :
   ---------------------------

   +5VIN  = VCC : 3 Amps
   +3V3IN = 3V3 : 3 Amps
   VEEIN  = -5V : 1 Amp


b) POWER SUPPLY CONNECTOR :
   ------------------------

   9-pin MCV-1.5 = SK30 / pin 1 : spare  -> LK33
           pin 2 : GND
           pin 3 : +5VIN  -> fuse FS1
           pin 4 : GND
           pin 5 : +3V3IN -> fuse FS2
           pin 6 : GND
           pin 7 : VEEIN  -> fuse FS3
           pin 8 : GND
           pin 9 : spare -> LK34

c) FUSES :
   -------

   Littelfuse 154005.DR = smd 5Amp fuses  FS1 = 5A : +5VIN
                 FS2 = 5A : +3V3IN
                 FS3 = 5A : VEEIN   

d) LEDs :
---------
      DS1 : yellow = external clock present
      DS2 : red    = SW2 set to select stand-alone clock

      DS3 : green  = VCC ( +5V )  on
      DS4 : green  = 3V3 ( +3V3 ) on
      DS5 : green  = VEE ( -5V2 ) on


e) EXPANSION / TEST / DEBUG HEADER PL4 ( 50-pin DIL HEADER ) :
--------------------------------------------------------------

ODD PINS :
----------
1   GND
3   LFTRIGINP+  Diff.LVDS Fast Trigger In+  U24/3    LK17/3
5   GND
7   LFTRIGOUTP+ Diff.LVDS Fast Trigger Out+ U34/6
9   GND
11   LFTRIGTINP  LVTTL Fast Trigger In       U33/2    LK17+LK18/5
13   LFTRIGTOUTP LVTTL Fast Trigger Out      U25/7
15   CONTTINP    LVTTL Control In      U30/4    LK12/9
17   BUSYTINP    LVTTL Busy In      U13/2    LK3/3
19   SPARETINP   LVTTL Spare   In      U13/2    LK20/1
21   JTAGSEL     J-TAG Source Select      U16/19+U15/1
          ( LOW to select External PC J-TAG inputs )

<23-37>   LCPLD-PC<0-7>     8x LVTTL CPLD In/Out   U9/<37-42>,44,45

39   EXTCK       External J-TAG Clock In   U16/15
41   EXTDI       External J-TAG Data In   U16/12
43   EXTMS       External J-TAG Mode Sel In   U16/13
45   EXTDO       External J-TAG Data Out   U16/3   
47   GND
49   MCLKTOUTP   Mixed Clock Out      U27/3

EVEN PINS :
-----------
2   GND
4   LFTRIGINP-  Diff.LVDS Fast Trigger In-  U24/2    LK18/3
6   GND
8   LFTRIGOUTP- Diff.LVDS Fast Trigger Out- U34/7
10   GND

<12-18>   MCONT<1-4>TOUTP     4x LVTTL Control      U30/11-14

<20-34>   LBUSY<1-8>TOUTP     8x LVTTL Busy      U6+8/12,14,16,18

<36-50>   LSPARE<1-8>TOUTP  8x LVTTL Spare   U5+7/12,14,16,18


f) CPLD U9 TEST HEADERS :
-------------------------

LH        8-pin SIL Header PL1      U9/<11-16>,<29-31>
Bottom        8-pin SIL Header PL3      U9/<60-68>   
RH        8-pin SIL Header PL5      U9/<91-98>
Top        8-pin SIL Header PL2      U9/<109-117>



SCHEMATICS, LISTS AND DOCUMENTS :
---------------------------------

THIS MANUAL :
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_CCC-MANUAL-3.txt

OVERALL CALICE DAQ ARCHITECTURE
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_CALICE-DAQ_Diag-1.ppt

HDMI SIGNALS
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_HDMI-SIGNALS_Diag-2.ppt

CCC PHOTO
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_PHOTO_Diag-3.ppt

CCC BLOCK DIAGRAM
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_BLOCK-DIAGRAM_Diag-4.ppt

ANNOTATED LAYOUT
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_ANNOTATED-LAYOUT_Diag-5.ppt

CIRCUIT DIAGRAMS :
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_pc3405m-Schematics.pdf

PCB LAYOUT and LINKS :
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_pc3405m1_Top-Silk.pdf

PCB - SETUP :
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C_LINKS-SETUP.txt

PCB - IC LIST :
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C-PCB_ICs_NEW-NOS.txt

PCB - CONNECTORS LIST :
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C-PCB_CONNECTORS_NEW-NOS.txt

PCB - LINKS LIST :
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C-PCB_LINKS_NEW-NOS.txt

PCB - EXPANSION INTERFACE HEADER SIGNALS LIST :
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C-PCB_PC-INTERFACE-SIGNALS_NEW-NOS.txt

PCB - EXTERNAL INPUT / OUTPUT SIGNALS LIST :
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C-PCB_SIGNALS_NEW-NOS.txt

PCB - CPLD U9 INPUTs/OUTPUTs LIST
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C-PCB_CPLD-INPUTS-OUTPUTS_NEW-NOS.txt

PCB - HDMI SIGNALS LIST
http://www.hep.ucl.ac.uk/~mp/CALICE_C-C/CALICE_C-C-PCB_HDMI-CONNECTIONS.txt

VHDL source for 'simple' firmware
ccc_simple_top.vhd
https://twiki.cern.ch/twiki/pub/CALICE/ClockControlCard/ccc_simple_top.vhd

Pinout file for Xilinx ISE
ccc.ucf
https://twiki.cern.ch/twiki/pub/CALICE/ClockControlCard/ccc.ucf

Details of the Serial Interface
https://twiki.cern.ch/twiki/bin/view/CALICE/CCCSerialInterface

Details of the Register List
https://twiki.cern.ch/twiki/bin/view/CALICE/CCCRegisterList



CPLD U9 TEST FIRMWARE DESCRIPTION
=================================

There is pre-programmed test setup which allows for testing
of the CCC board.


Simple Firmware for CCC Post-Production Testing
-----------------------------------------------

This makes use of the rotary switch SW1 to configure IO on the
board in different ways :

0       Ins (ORed) to Outs.
        Busy out <= OR( in<8:1> )
        Control out <= OR ( in<4:1> )
        Spare out <= OR( in <8:1> )
        Fast Trig out <= in
        RS232 out <= in
        Clock Delay <= 0
        EXIO<0> <= Clock0
        EXIO<1> <= Clock1
        EXIO<2> <= Clock2
        EXIO<3> <= Delayed Clock
        EXIO<4> <= ClockOn?
        EXIO<7:5> <= 2b000

        Debug Headers: right <= left, bottom <= top

1    12.5MHz clock on all single outputs, 12.5MHz counter on all busses
2    Same as 1. above, but with a slow count on delay (2s-ish/period)
3-e    All 'Zeros'
f   All 'Ones' on outputs


VHDL source for 'simple' firmware :
-----------------------------------
ccc_simple_top.vhd

https://twiki.cern.ch/twiki/pub/CALICE/ClockControlCard/ccc_simple_top.vhd


Pinout file for Xilinx ISE :
----------------------------
ccc.ucf

https://twiki.cern.ch/twiki/pub/CALICE/ClockControlCard/ccc.ucf


JTAG file for programming CPLD :
--------------------------------
ccc_simple_top.jed

https://twiki.cern.ch/twiki/pub/CALICE/ClockControlCard/ccc_simple_top.jed



RUN FIRMWARE DESCRIPTION
========================

Firmware for Running
--------------------

Firmware allowing interfacing to a PC is developing.
It makes use of the the RS232 port for connection to the PC.


Details of the Serial Interface are on the CCCSerialInterface page :

https://twiki.cern.ch/twiki/bin/view/CALICE/CCCSerialInterface


There is also the description of the REGISTERS on the on-board
CPLD U9, which can be read-out using the RS232 link :

https://twiki.cern.ch/twiki/bin/view/CALICE/CCCRegisterList


This firmware also contains some debug modes, selected using of the
hex switch SW1.

Hex-switch settings :
---------------------
8       cont, ftrig, spare & busy <= 0, delay <= "000000"
9       cont, ftrig, spare & busy <= 1, delay <= "111111"
A       cont, ftrig, spare & busy <= clk, delay <= "010101"
others  All 'Zeros'




                          This version : MP & MW, UCL, 08 Apr. 2009


                                Previous versions :    08 Apr. 2009
                         29 Mar. 2009
                         23 Mar. 2009
                         25 Feb. 2009
                         23 Feb. 2009
                         22 Jan. 2009
                         21 Jan. 2009
                         20 Jan. 2009
                         19 Jan. 2009
                         16 Jan. 2009
                         12 Jan. 2009



-- MattWarren - 04-Dec-2009
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Topic revision: r1 - 2009-12-04 - Warren
 
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