Overview

The International Linear Collider project involves new constraints on front-end electronics. To fulfil the requirements of a digital hadronic calorimeter, a very high granularity is needed: a number of channel as high as 50 millions is expected. The low total power budget (about 2 kW for the HCAL) and the inability to cool front end electronics due to lack of space leads to drastically reduce the dissipated power of the analog front-end electronics. Moreover, the most important part of signal processing will be embedded inside the detector for compactness and reduce the number of outgoing wires. The development of a mixed-signal readout ASIC with digital memory is compulsory to achieve technical requirement of the digital hadronic calorimeter. In order to prove the feasibility of such a calorimeter, the CALICE collaboration plans to build a prototype of cubic meter.

The DIRAC ASIC development has been driven by the following constraints:

  • Reduce the power consumption as low as possible;
  • Reduce the price amount, by selecting cheap technology and have a tiny silicon area;
  • Try to suppress all calibration needs, not compulsory for a two bits calorimeter;
  • Decrease detector PCB complexity.

This 64 channel ASIC will be used to compare the behaviours of gaseous detectors Glass-RPC, Micromegas and eventually GEM.

Status

Here are the main features of this ASIC (v2):
  • Low-cost Austriamicrosystem 0.35 μm CMOS technology;
  • Low-power (1 mW per channel) with power pulsing @1%: < 10 μW per channel;
  • 2 gains: 100 mV/pC (RPC mode) and 5 mV/fC (MicroMegas/GEM mode);
  • 3 programmable thresholds, 8 bits on 1 V (3.9 mV/DAC code) or 40 fC/DAC code and 0.8 fC/DAC code;
  • 2-bit bunch crossing identifier (BCID);
  • 8 events internal memory.
Tests on bench have given the following performances (v1):
  • Noise on threshold: 2.4 fC (@ 5 σ);
  • Minimum threshold: 8 fC;
  • Threshold dispersion: 2 fC (one channel) or 16 fC (64 channels);
  • Linearity: better than +/- 0.8 fC;
  • Power-on time: less than 1 μs.

The first prototype has successfully been tested with a Micromegas detector in beam at CERN SPS (H2B line, north area) in august 2008. Beam profile and scanning with 200 GeV pions have been observed. The second prototype has slightly improved performances, and a stack of 8x8 MICROMEGAS chamber has been beam-tested in november 2009.

Future develoments

The second version of the DIRAC ASIC has been submitted to foundry in october 2008. It includes some modifications and improvements: a malfunctioning of the trigger system has been corrected, a channel masking feature has been added, LVDS clock receiver has been included, an analog readout capability and internal test circuitry have been added. Moreover, two supplementary Micromegas gain of 1.6 fC/DAC code and 3.2 fC/DAC code have been implemented.

The ASIC will be tested in the 1Q 2009, and a low volume production (about 200 chips) in TQFP 120 package is expected to equip a square meter. After uniformity and efficiency tests, the behaviour of the detector and the chip will be tested in hadronic showers.

Ressources

Publications

  • DIRAC: A DIgital Readout Asic for hAdronic Calorimeter, IEEE-NSS conference record, DOI: 10.1109/NSSMIC.2008.4774745
  • JINST_003P_0809

More information

Presentations:

Photo gallery

  • Active Sensor Unit with DIRAC ASIC:
    img_2297.jpg

  • Die of DIRAC ASIC:
    image8.jpg

-- RenaudGaglione - 19 Dec 2008

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Topic revision: r9 - 2010-01-27 - RenaudGaglione
 
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