ECAL DIF Information

The Detector Interface forms the bridge between the Very Front-End (VFE) chips integrated in the detector slabs, and the DAQ system. The connection with the DAQ is established by a LDA-DIF link, running over AC-coupled LVDS differential pairs on standard HDMI cables and connectors.

The HDMI connector on the EDIF has the following pinout:

Pin Signal Signal Pin Signal Signal
Number Name Description Number Name Description
1 L2D_CLK+ LDA to DIF LVDS Clock + 2 RG1 L2D_CLK shielding
3 L2D_CLK- LDA to DIF LVDS Clock + 4 L2D_DATA+ LDA to DIF LVDS Data +
5 RG2 L2D_DATA shielding 6 L2D_DATA- LDA to DIF LVDS Data -
7 D2L_DATA+ DIF to LDA Data + 8 RG3 D2L_DATA shielding
9 D2L_DATA- DIF to LDA Data + 10 D2L_SPARE+ DIF to LDA Spare +
11 RG4 D2L_SPARE shielding 12 D2L_SPARE- DIF to LDA Spare -
13 2V5 2V5 power for HDMI add-ons 14 3V3 3V3 power for HDMI add-ons
15 L2D_SPARE+ LDA to DIF Spare + (not shielded) 16 L2D_SPARE- LDA to DIF Spare - (not shielded)
17 RG5 HDMI shield 18 GND Ground (for power)
19 GND Ground (for power)      

NOTE that power is supplied on pins13 and 14, with accompanying GND on 18,19, by the DIF. Historically these pins were reserved to power external hardware for driving the LDA-DIF link if necessary. They should be Not Connected at the LDA end.

The DIF is connected with the slab, or, the intermediate board at the end of the slab, by a 90 pin connector of the following type:

  • DIF: SAMTEC FSH of the 145-04-L-DH-SL
  • Slab: SAMTEC SFMH 145-02-L-D-LC
The pinout of the DIF-Slab connector in xls format.

Dif prototype (version 1)

DIFexpl.jpg
ECAL DIF v1

Explanation of the DIF components indicated in the picture above:

  1. JTAG programming header
  2. HDMI connector for LDA-DIF link
  3. DIF-DIF link connector
  4. Mini-USB connector
  5. PROM for Xilinx FPGA
  6. Cypress SDRAM 2MB, 10ns
  7. FPGA Xilinx Spartan3-1000
  8. USB interface chip
  9. User connector header
  10. FPGA reload pushbutton
  11. 90pin DIF-Intermediate board or Slab connector

For this DIF prototype, it was assumed that all power regulation hardware is located at the end of the slab, or, alternatively, on a intermediate board between the DIF and the slab. Therefore, power is supplied through the designated pins on the 90 pin interface connector. The User Constraints File for the DIF FPGA can be found here

Dif production prototype (version 2)

difII-CC crop.jpg
ECAL DIF v2 on a standard sized card

Schematics of the DIF version 2 can be found here, with the schematics for the ac-coupling of LDVS pairs here

The ECAL DIF v2 has regulators to generate 2V5 and 1V2 from the 3V3 supply. the jumper settings on J3 and J4 determine whether the on-board regulators are used to supply the DIF. Note that when the regulators are active, the voltages will also appear on the slab connector. Power is supplied through the power connector at the bottom left in the picture, or through the slab connector, similar to DIF v1.

EDIF Firmware for throughput tests

edif_thruput_test.tar.gz

Hardware list

DIF ID location Comments
01 Cambridge batch proto, tested OK
02 Cambridge batch proto, tested OK
03 LLR @test1
04 LLR @test1
05 LLR @test1
06
07 LLR @test1
08
09
10
11
12
13
14 LLR @test1
15 LLR @test1
16 LLR @test1
17 LLR @remi FAIL
18
19
20
21
22
23 LLR @test0 SLAB #1 4xspiroc2A
24 LLR @test1
25 LLR @test1
26 LLR @test1
27 LLR @test1
28 LLR @test1
29 LLR @test1
30 LLR @test1
31 LLR stoc
32 LLR @test0 SLAB #3 4*spiroc2 + wafer
33 LLR stoc
34 LLR @test0 SLAB #2 1*spiroc2 +wafer
35 LLR stoc
36 LLR stoc
37 LLR stoc
38 LLR stoc
39 LLR stoc
40 LLR stoc

-- BartHommels - 04-Mar-2010 -- RemiCornat - 08-Nov-2011

Topic attachments
I Attachment History Action Size Date Who Comment
Microsoft Excel Spreadsheetxls DIFPinoutv52.xls r1 manage 28.0 K 2010-03-08 - 11:04 BartHommels DIF-Slab connector pinout
JPEGjpg DIFexpl.jpg r1 manage 648.9 K 2010-03-08 - 11:06 BartHommels DIF v1
PDFpdf Dif2_schematics.pdf r1 manage 44.8 K 2010-03-04 - 16:42 BartHommels Schematics of the DIF v2
Unknown file formatucf ECALDIF.ucf r1 manage 14.3 K 2010-03-17 - 16:27 BartHommels User Constraints file for the EDIF FPGA
PDFpdf acterm.pdf r1 manage 11.5 K 2010-03-17 - 15:57 BartHommels AC termination for LVDS circuit diagram
JPEGjpg difII-CC_crop.jpg r1 manage 220.0 K 2010-03-04 - 17:00 BartHommels Picture of DIF v2 on a standard sized card
Unknown file formatgz edif_thruput_test.tar.gz r1 manage 159.6 K 2011-09-07 - 18:13 BartHommels Firmware archive for throughput tests of ECAL DIF
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Topic revision: r9 - 2012-07-05 - BartHommels
 
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