-- RemiCornat - 13-May-2011

The DIF firmware is NOT STABLE. It is constantly updated, existing features are kept when possible (backward compatibility). The specifications stated above may differ from DIF task force old documents.

General condiderations

DIF can receive FAST commands, Bloc Transfer commands and raw data. Each valid command must be acknoledged (reset of command register) by the end user function triggered by the command.

Bloc transfert command are identified using : packet type = 0x2, type modifier = register ID, first data word (set a bit in the register)

Location to store/send row data is given by packet type and type modifier (equivalent to a 28b address).

The 4 MSB of the packet type are used for the DCC nibble (identification of port used on DCC).

Common FAST Commands

Those fast commands are common to every detectors. If the automatic acknoledge option is selected (hardcoded in DIF_pack.vhd), the DIF generates an acknoledge packet (with packet ID 0xBABA).

Name Data Usage Comments Ack
Reset BCID 0x21 (D1.1) Generates a global reset on the DIF Not compliant with specs No
ACQ start int 0x22 (D2.1) Generates a packet from the content of the test FIFO Not compliant with specs Auto
ACQ start ext 0x42 (D2.2) Opens the Acquisition gate Auto
ACQ stop 0x62 (D2.3) Force closing acquisitino gate Auto
ReadOut cont 0x43 (D3.2) NOT USED Not compliant with specs Auto
ReadOut stop 0x23 (D3.1) NOT USED Not compliant with specs Auto
LSLINK resume 0x6F (D15.3) TEST Not compliant with specs Auto
LSLINK pause 0x8F (D15.4) TEST Not compliant with specs Auto

Common bloc transfert commands

Name Modifier Bit map
RESET 0x0004 7: monitoring clear, 3: ROC reset bcid, 2: ROC resetb, 1: ROC reset probes, 0: ROC reset slow control

Name Modifier Bit map
MODE 0x0006 15: enable clock synchronization mode, 0: read MODE register

Name Modifier Bit map
SC 0x000A 0: enable RAM1

Name Modifier Bit map
RO 0x000E 12: Read RAM1

bit 12, needs RAM1 enable

Name Modifier Bit map
READ_STATUS 0x0012 1: Read status1, 0: read status0

Name Modifier Bit map
SPILL 0x001C 2: Read register bank BORB3, 1: read register bank BORB2, 0: read register bank BORB1

command to be renamed.

Packet to send to the DIF :

Word Content Comment
Type 0x0002 Common block transfert command
ID don't care
Modifier according to tables above
Size 0x0001
Data Set appropriate bit onehot

Specific commands

Not implemented.

CORE functions

The DIF core includes I/O interfaces (USB and serial link), provides commands decoding (and acknoledge managment), downstrem and upstream data paths and supervisor functions.

MODE register bank

This register bank configures the DIF CORE and has 4 16b registers given below :

reg# bitmap
1 15-6:N/C, 5 : disable power pulsing, 4: N/C, 3: enable Messages, 2: enable LSLINK flow control, 1: Disable FCMD auto-echo 0:N/C
2 16b user programmable DIF_ID
3 15-12:N/C, 11-8:received DCC nibble, 7-0: APROBE channel number (temp)
4 16b firmware revision (read only) hardcoded in DIF_local package

Write : DATA type packet with MODE modifier (0x0001 0x---- 0x0006 0x0004 data1 ... dataN)

Read : BTCMD MODE, bit 0 (0x0002 0x---- 0x0006 0x0001 0x0001)

STATUS0 register bank

11 registers

reg# bitmap
1 DIF state
2 ROC status (RO)
3 ROC status (SC)
4 BUFFER status
5 QUEUE status
6 Number of timeout ramfull/chipsat
7 Number of timeout readout
8 Number of timeout transmiton
9 Number of received packets
10 Number of bad packets (CRC check)
11 Number of transmit packets

STATUS1 register bank

Gives BTCMD status, 16 registers

Shared resources


16bx4096 RAM, can store slow control data for about 50 chips.

The 8 lsbs are used to store SC data.

The 8 MSBs are filled with SC data read back from chips, should load SC data twice in ROC to be able to read back same data.

Read back the ram after SC load in order to check content.

Debug FIFO

A FIFO is accessible through DAQ interface for tests purpose. No internal access is provided (to be changed soon). To write data in the test fifo, sent packets of type “data” and “SC” modifier (0x0001, 0x----, 0x000A, size, data). The FIFO can be read using FCMD 22 (start_acquire_int) or sending a CMD_ECAL packet with modifier 0x0001 (packet : 0x0010 0x---- 0x0001 0x0001 0x0001).

Pseudo Random Pattern Generator

Used to emulate data from detectors. Generates a pseudo random 16b words stream. The number of packets, the size of packets and the gap in time between packets can be specified (see BoRB 3).

USER REGISTERS : Bank of Register banks (BoRB)

3 register banks of respectively 4, 1 and 4 registers.

BoRB1 : configuration of detector driver

Reg ID Usage Comments
1 Chip type 8: ROC select reg, 7..0: Chip type
2 acquisition mode 7: beam clk, 6: testbeam
3 N/C not in use
4 Number of chips bits 7 to 0

BoRB2 : debug, shoud/must remains tied to 0

BoRB3 : Configuration of pseudo random data generator

Reg ID Usage Comments
1 inter packet delay 16bits, number of slow clock periods
2 enable bit 0
3 number of packets bits 8..0
4 Packets size bits 8..0

FLASH RAM driver

Upstream path

Path to used to send data to the DAQ. 3 levels of entry points : QUEUE (encapsulated packet), BUFFER (packets), SOURCE (data stream).

3 primary sources are multiplexed, listed by order of priority : pseudo random generator, RAM1 and detector driver.

All other data are sent at the QUEUE entry point and will be selected thanks to an automatic round robbin logic (no precedence).

read-out data format

One spill = one acquisition gate

ACQid : identifier of spill, incements on start acquisition

id : a number of chip which sends data, incements on transmitON falling edge

nbchip : total number of chips having sent data

SIZE : total number of raw data words (16b)

section subsection word hex ascii
SPILL header   marker FFFC ..
    ACQid MSB .... ..
    ACQid lsb .... ..
      5053 SP
      4C49 IL
    blank space 2020  
N times CHIP header marker FFFD ..
    FF id FF.. ..
      4843 CH
      5049 IP
    blank space 2020  
  CHIP trailer marker FFFE ..
    FF id FF.. ..
    blank space 2020  
    blank space 2020  
SPILL trailer   marker FFFF ..
  ACQid MSB .... ..
  ACQid lsb .... ..
    00 00.. ..
  SIZE MSB .... ..
  SIZE lsb .... ..
    blank space 2020  

The SPILL header is pushed in the buffers when receivinf a FCMD startSPILL. The SPILL trailer is pushed in the buffer when the signal end_readout from ROCs is caught by the DIF.

The CHIP header and trailer correspond to the falling and rising edges of transmit on.

Integration of new user functions

  • Define list of fast commands
  • Define list of commands
  • Define list of parmeter registers
  • Define input data (ie. specific packet type and type modifiers for the function)
  • Choose one method for data output (if relevant) : buffer, queue or direct
  • Define external interfaces
  • Develop stand alone HDL up to a working simulation
  • Integration of new code in the DIF framework should be done at LLR (~3 weeks, full time)
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Topic revision: r7 - 2013-12-11 - RemiCornat
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