The DIF firmware is NOT STABLE. It is constantly updated, existing features are kept when possible (backward compatibility). The specifications stated above may differ from DIF task force old documents.

General condiderations

DIF can receive FAST commands, Bloc Transfer commands and raw data. Each valid command must be acknoledged (reset of command register) by the end user function triggered by the command.

Bloc transfert command are identified using : packet type = 0x2, type modifier = register ID, first data word (set a bit in the register)

Location to store/send row data is given by packet type and type modifier (equivalent to a 28b address).

The 4 MSB of the packet type are used for the DCC nibble (identification of port used on DCC).

Common FAST Commands

Those fast commands are common to every detectors. If the automatic acknoledge option is selected (hardcoded in DIF_pack.vhd), the DIF generates an acknoledge packet (with packet ID 0xBABA).

Common bloc transfert commands

bit 12, needs RAM1 enable

command to be renamed.

Packet to send to the DIF :

Specific commands

Not implemented.

CORE functions

The DIF core includes I/O interfaces (USB and serial link), provides commands decoding (and acknoledge managment), downstrem and upstream data paths and supervisor functions.

MODE register bank

This register bank configures the DIF CORE and has 4 16b registers given below :

Write : DATA type packet with MODE modifier (0x0001 0x---- 0x0006 0x0004 data1 ... dataN)

Read : BTCMD MODE, bit 0 (0x0002 0x---- 0x0006 0x0001 0x0001)

STATUS0 register bank

11 registers

STATUS1 register bank

Gives BTCMD status, 16 registers

Shared resources

RAM1

16bx4096 RAM, can store slow control data for about 50 chips.

The 8 lsbs are used to store SC data.

The 8 MSBs are filled with SC data read back from chips, should load SC data twice in ROC to be able to read back same data.

Read back the ram after SC load in order to check content.

Debug FIFO

A FIFO is accessible through DAQ interface for tests purpose. No internal access is provided (to be changed soon). To write data in the test fifo, sent packets of type “data” and “SC” modifier (0x0001, 0x----, 0x000A, size, data). The FIFO can be read using FCMD 22 (start_acquire_int) or sending a CMD_ECAL packet with modifier 0x0001 (packet : 0x0010 0x---- 0x0001 0x0001 0x0001).

Pseudo Random Pattern Generator

Used to emulate data from detectors. Generates a pseudo random 16b words stream. The number of packets, the size of packets and the gap in time between packets can be specified (see BoRB 3).

USER REGISTERS : Bank of Register banks (BoRB)

3 register banks of respectively 4, 1 and 4 registers.

BoRB1 : configuration of detector driver

BoRB2 : debug, shoud/must remains tied to 0

BoRB3 : Configuration of pseudo random data generator

FLASH RAM driver

Upstream path

Path to used to send data to the DAQ. 3 levels of entry points : QUEUE (encapsulated packet), BUFFER (packets), SOURCE (data stream).

3 primary sources are multiplexed, listed by order of priority : pseudo random generator, RAM1 and detector driver.

All other data are sent at the QUEUE entry point and will be selected thanks to an automatic round robbin logic (no precedence).

read-out data format

One spill = one acquisition gate

ACQid : identifier of spill, incements on start acquisition

id : a number of chip which sends data, incements on transmitON falling edge

nbchip : total number of chips having sent data

SIZE : total number of raw data words (16b)

The SPILL header is pushed in the buffers when receivinf a FCMD startSPILL. The SPILL trailer is pushed in the buffer when the signal end_readout from ROCs is caught by the DIF.

The CHIP header and trailer correspond to the falling and rising edges of transmit on.

Integration of new user functions

• Define list of fast commands
• Define list of commands
• Define list of parmeter registers
• Define input data (ie. specific packet type and type modifiers for the function)
• Choose one method for data output (if relevant) : buffer, queue or direct
• Define external interfaces
• Develop stand alone HDL up to a working simulation
• Integration of new code in the DIF framework should be done at LLR (~3 weeks, full time)