NOTE: All data fields are in Network Byte Order. Since electronics lives in the real world after all...


  • 20 LDA baseboards (known as MD2)
  • 20 HDMI v2 boards
  • 15 Ethernet v2 boards (no TLK2501 chipset) + 5 Ethernet v1 boards
  • 10 HDMI v1 boards (with DC coupling, backwards connector - NOT WORKING )

See HardwareList for list boards and locations.


MD2 and HDMI board

Switches on the MD2.
There are 8 small switches on the MD2 base board, when set to ON they ground the input, and when off it floats to VCC. This is the reverse of what is expected, but thats life.
They are used currently for the following tasks.

  • SW1: Clk as the StartupFPGA->MainFPGA DIF clock (Used when running stand alone)
    • 1=2x
    • 0=1x
  • SW3-2: Selects clock source as DIF clock.
    • "00" = CLOCK1
    • "01" = CLOCK2
    • "10" = 25MHZ
    • "11" = 10MHZ (Not supported as DCM cannot lock to this)
  • SW4: Unused... currently but might select Standalone or CCC operation
  • SW5: Autonegotiation on ODR Link
    • 1 = Disable (Defaults to Full Duplex 1000-baseX
    • 0 = Enable (Can be connected via CAT5 to switch in this mode)
  • SW6: Main FPGA bitstream source
    • 1 = SPI Flash
    • 0 = Platform Flash (Default usage, easier to do, but future LDAs will not have Platform Flash)
  • SW7: SPI WP mode (Used to stop the SPI getting corrupted during normal usage)
    • 1 = Write Protect
    • 0 = Write Enabled
  • SW8: Master JTAG Socket routing
    • 0 = Socket is connected to Main FPGA
    • 1 = Socket is connected to the 2nd SPI flash chip, iMPACT direct SPI programming is possible in this mode (Observe SW7's settings.)

LEDs on the MD2 board are next to the power connector

  • LED1: Ethernet logic is in RESET mode (due to startup, no RX lock or other reason).
  • LED2: Ethernet data seen, packets flash the LED.
  • LED3: Ethernet Link is up (Autoneg has completed if enabled).
  • LED4: MAC address has been received from the Startup_FPGA, which got it from the One-Wire prom.
  • LED5: RX 125Mhz DCM has locked succesfully, if not lit.. there is major issues..
  • LED6: DIF Clk DCM is locked (Standalone DIF clock will be seen by main FPGA).
  • LED7: Main FPGA is programmed (Startup FPGA is responsible for flash loading the main one).
  • LED8: Main FPGA is ready and responding. (Startup FPGA has also loaded MAC from One-Wire prom)

PS2 Socket (U35) is used to drive reset and firmware reload.

  • Pin 3 and the Shield are Ground.
  • Short Pin 5 to Ground for MainFPGA firmware reload.
  • Short Pin 2 to Ground for Master Reset.

These are de-bounced inside the FPGA, and a simple push button switch is enough, I use a hacked PS2 cable with two momentary push buttons soldered on the end.

There are also LEDs on the Ethernet board, but we will not use these anymore

JTAG Cable for Startup FPGA
There is a slight issue with this, namely that the TDI and TCLK lines are swapped, so you will need a custom cable to access this.

Ethernet Board

*Correct Jumper Settings for his board*
The above photo is not to be used as reference, but the following diagram is correct.


Technical Information

LDA Packet Format

The LDA is built on standard Ethernet. Communication to and from it is done via RAW Ethernet packets

Dst MAC Src MAC Ethernet Type LDA_Type LDA_Modifier LDA_PktID LDA_DataLength LDA_Data PAD CRC32
6 Bytes 6 Bytes 2 Bytes 2 Bytes 2 Bytes 2 Bytes 2 Bytes Variable Pad to Min Ethernet Size 4 Bytes

Ethernet Types used. These are generally not used in the real world, so we chose them at random. Packets with a different Ethernet Type will be ignored.

Hex Value Type
0x0809 Fast Command Packet
0x0810 Normal LDA Packet
0x0811 DIF Data Packet

LDA_Types Used. This is split into 2 bytes, the upper and lower. The Upper is used to encode a subsystem inside the LDA, the lower is used to encode the operation type. Some of these are ODR->LDA others are LDA->ODR

Sub System Encoding

Value Sub System Direction
0x00 LDA Registers Both
0x01 DIF Transport Both
0x02 Diagnostic Memory Both
0xFF LDA Packet Generator LDA->ODR

Operation Encoding

Value Operation Direction
0x00 LDA PktGenData LDA->ODR
0x01 Write ODR->LDA
0x02 Read ODR->LDA
0x03 Write ACK LDA->ODR
0x04 Read Reply LDA->ODR
0x05 Read NACK LDA->ODR
0xFF LDA Saw Bad Packet LDA->ODR

LDA_Modifier is used to indicate things such as which DIF link a DIF packet should be sent down, that is currently the only use of it. 0xFFFF indicates a broadcast down all DIF links that are currently operational.

LDA_PktID is used to track Replies to things. For example a any LDA register operations will result in a reply, these replies will have the same PktID in them.

LDA_DataLength is a measure of how many objects there will be in the LDA Data array. For Register operations on the LDA it is the total number of LDA Register Packets that follow. For DIF operations it is the Number of DIF Packets that follow. For DIF Event data it is the Number of Event Packets that follow.

CRC32 This is not really a user accessible data field. Normally the MAC layer on the Ethernet card will add this, and will strip it on received packets. However, depending on the operation it may or may not be visible and so is included in this definition for completeness.

Any packets the fail the CRC32 check on RX at the LDA will be silently dropped.

LDA Register Packet Format

Access to LDA registers is done via the following sub packet type.

Address Data
2 Bytes 4 Bytes

Address is 16 bits, and in general fill all unused data with 0x0 Data is 32 bits, even though most registers are 16. This is to allow future expansion.

Lower bits of data are used first, so a register that returns < 32 bits will return it in the lower bits of the data space, the same for writes.

When performing a Read the packet must still include the space for the data, even though it will be over written by the LDA internal processing. This just makes things more symmetric for both reads and writes.

You can pack as many register sub packets as you want into an lda_packet. However, they will all be of the same type, eg, all READ or all WRITE, you cannot currently mix them.

LDA DIF Event Packet Format

When Events come into the LDA from the DIF they are wrapped in an LDA packet before being sent onward to the ODR. They are dropped verbatim into the LDA_Data block of the packet. The LDA-DIF Link CRC is retained, so that software can check it if needed.

LDA_Type Will have the upper portion set to DIF Transport and the lower 8 bits set to show which DIF Link it came from. LDA_PktID Will be the serial number of the packet, which will increase each time, allowing some way to see if there are missing ones. LDA_DataLength Will show the number of encapsulated DIF Packets

Future enhancement might be the addition of a flag to say if the packet from the DIF passed the CRC or not

LDA Memory Map

Memory access's to registers inside the LDA are done using a 16bit address. This address is then subdivided into a Block and Register range.
The upper 4 bits define the Block
The lower 12 define the Register

LDA Register Address Space














































































LDA Fast Command Packet Format

Fast commands are generated via two mechanisms. The first is in direct response to various hardware inputs from the CCC into the LDA and the second is manually via the LDA-ODR link.

When done via this method the packet used is smaller than the normal LDA packet format, and is processed separately.

Dst MAC Src MAC Ethernet Type Command_Word DIF_Link Comma Data Parity PAD CRC32
6 Bytes 6 Bytes 2 Bytes 2 Bytes 2 Bytes 1 Byte 1 Byte 2 Bytes Pad to Min Ethernet Size 4 Bytes

Ethernet Type is set to 0x0809 for Fast Commands. The reason for this is that the MAC layer in the LDA has a filter to syphon off those packet types.

Command Word is set to a constant. Currently defined as 0xFA57.

DIF_Link A mask which defines which port the command is for. A value of 0xFFFF would be used as a broadcast to all currently active DIF links.

Comma defines which comma character to use

Data defines which byte to send as the data byte.

Parity is a simple check, the bits of this are defined as follows.

Bit Data Used
0 Lower 8 bits of Command_Word
1 Upper 8 bits of Command_Word
2 Lower 8 bits of DIF_Link
3 Upper 8 bits of DIF_Link
4 Comma
5 Data

We use an Even Parity scheme, and the reason for using this is that the command is recognised almost as soon as the parity is validated, rather than waiting for the full CRC32 to be verified.

Future operations may use a different Command_Word for other usage.


-- MattWarren - 30-Aug-2011

-- MarcKelly - 20 Jan 2009

Topic attachments
I Attachment History Action Size Date Who Comment
JPEGjpg Ethernet_board_jumpers.jpg r1 manage 10.8 K 2009-06-26 - 17:09 MarcKelly Correct jumpers for Ethernet board
PDFpdf GigE_Board.pdf r1 manage 3981.0 K 2010-02-19 - 11:44 Warren Ethernet v1 Schematics
PDFpdf HDMI_Board.pdf r1 manage 4843.5 K 2010-02-19 - 11:45 Warren HDMI v1 Schematics
JPEGjpg LDA_Eth.jpg r1 manage 161.1 K 2009-06-25 - 12:17 MarcKelly LDA Ethernet Board with TNET, TLK and USB
PDFpdf MD2_Board.pdf r1 manage 8146.3 K 2010-02-19 - 11:43 Warren MD2 Schematics
PDFpdf MU1_HDMI_ISSUE2.pdf r1 manage 3641.0 K 2010-02-19 - 11:42 Warren HDMI v2 Schematics
PDFpdf MU2_COMMS_ISSUE2.pdf r1 manage 2585.8 K 2010-02-19 - 11:43 Warren Ethernet v2 Schematics
JPEGjpg lda_and_hdmi.jpg r1 manage 188.0 K 2009-06-25 - 12:22 MarcKelly MD2 Board and HDMI interface
Unknown file formatgz lda_src.tar.gz r1 manage 11750.4 K 2011-08-30 - 17:52 Warren LDA source (including .bit and .mcs files)
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