ODR Firmware Description

Authors Barry Green and Matt Warren

Project Related files

Scripts have been written to avoid some of the annoyances of Xilinx IDE (The GUI part of Xilinx ISE). The scripts allow all intermediate files to be stored in scratch space. They also allows a comment to be added to an index of .mcs files. They will also send a mail when the build is complete with information about how successful the build was. If the build is run in a "screen" terminal then the build can be monitored from anywhere.

  • Usage example: ./Setup-rhul.sh "PCIe version changed to 0x31"

  • RHUL Build script
    • File: Projects/QuadMake/setup-rhul.sh
    • Status: might not work at first attempt due to missing guide file
    • Description: This script is run to start the build of the ODR firmware. This file set environment variables which are relevant to the RHUL site. The generic build script is called at the end of this script.

  • UCL Setup Script
    • File: Projects/QuadMake/setup-ucl.sh
    • Description: This file sets environment variables relevant to the UCL site. Once these have been set the generic build has to run manually.

  • Generic Build Script
    • File: /Projects/QuadMake/GenericBuild.sh
    • Description: The generic build script is called by both the site specific build scripts. This set up some variables which are common to both sites. It then calls make.

  • Source List Script
    • File: Projects/QuadMake/SourceList.sh
    • Description: This lists the VHDL files used by the project. This file is sourced by the GenericBuild.sh script

  • Makefile
    • File: Projects/QuadMake/Makefile
    • Description: The Makefile is used by make whichis called by the GenericBuild script. It runs the synthesis, mapper, place and route, and creates the PROM file. It might be better done in a script as it is very rare for files to be changed which don't make all of the build re-run.


Contraints

Warning: Can't find topic CALICE.TopVHDLStructure_4x125_V4fx_DualUcf


Coregen Cores

  • DMA Done FIFO
    • Coregen Source File: Stage1/Coregen_cores/DMADoneFIFO.xco
    • Coregen core File: Stage1/Coregen_cores/DMADoneFIFO.ngc
    • Description: When the Primary DMA transfer has completed it writes information about this transfer to the DMADoneFIFO. This will include information such as location, size and event ID. There is also additional debugging information like the start and end addresses in buffer memory.

  • Free Page FIFO
    • Coregen Source: Stage1/Coregen_cores/FreePageFIFO.xco
    • Core file: Stage1/Coregen_cores/FreePageFIFO.ngc
    • Description: 32 bit FIFO with output fall through. Fall through also means that FIFO has two clocks. An alternative would be a single clock FIFO with a fall through state machine on the output.


Top Level

VHDL Files

  • Addresses and global types
    • File: Addresses/addresses_quad.vhd
    • Package: global_types
    • Status: Might need some tidying and improvement to generic support
    • Description: This is the central place where values which are also used by the drive can be stored. Global variables and enumerated types are defined here.

  • Register64
    • File: Stage1/Register64/Register64.vhd
    • Entity: Register64
    • Status: Could be modified to use a core
    • Description: This is a 64 bit register with a write enable and two output buses. One for reading back the register contents. It is used many places, even when 64 bits are not required, relying on optimization to remove the unused parts.

  • PCIe Lite x4 Core
    • File: Stage1/PCIe-lite/core/synthesis/xilinx/vhdl/pcielite_x4_125_xilinx_board_eval.vhd
    • Entity: Multiple entities
    • Status: Supplied by PLDa. This is the latest version which doesn't require a license.
    • Description: This is part of the PCIe lite core supplied by PLDa

  • EZ Xilinx Board Evaluation
    • File: Stage1/PCIe-lite/core/synthesis/xilinx/vhdl/ez_xilinx_board_eval.vhd
    • Entity: Multiple entities
    • Status: Part of PLDa PCIe core
    • Description: This is part of the core supplied with the evaluation board.

  • PHY for the Xilinx evaluation board
    • File: Stage1/PCIe-lite/phypcs/synthesis/xilinx/vhdl/phypcs_xilinx_board_eval.vhd
    • Entity:
    • Status: Part of the PLDa core
    • Description: This supplies the PHYs for the PCIe interface

  • PCIe Core X4
    • File: Stage1/PCIeBridge/PCIeCorex4.vhd
    • Entity: PCIeCorex4
    • Status:
    • Description: This was originally created by the PLDa wizard. It sets parameters for the PCIe lite core. It is as easy to set them up by hand with the help of the documentation.

  • PCIe x4 PHY
    • File: Stage1/PCIePHY/PCIePHYX4.vhd
    • Entity: PCIePHYx4
    • Status:
    • Description: This is implemented to connect the PCIe core to the PCIe PHY. It does very little, but but it provides a useful division between then core and the rest of the code.

  • PCIe Bridge
    • File: Stage1/PCIeBridge/PCIeBridgeX4.vhd
    • Entity: PCIeBridgeX4
    • Status:
    • Description: This interfaces the PCI Interface to the PCIe core. It performs a few functions. It sets the read latency on the local bus for accesses from different BAR regions. It sets up DMA0, which is used to return data when doing reads.

  • PCIe Interface X4
    • File: Stage1/PCIeInterface/PCIeInterfaceX4.vhd
    • Entity: PCIeInterfaceX4
    • Status: PCIe Interface and PCIe Bridge could probably be merged.
    • Description: This provides an interface to the PCIe Bridge. It add some reset functionality.

  • S-link LDC Emulation
    • File: Stage1/DataGenerator/ldcEmu.vhd
    • Entity: ldcEmu
    • Status: May need changing to match the expected CALICE data format.
    • Description: This code was lifted from the Atlas Robin. It generates data with incrementing event ID.

  • Test Points
    • File: Stage1/TestPoints/TestPoints.vhd
    • Entity: TestPoints
    • Status:
    • Description: This maps schematic signal names to pins of the connectors on the matrix

  • Slave Address Decoder
    • File: Stage1/SlaveAddressDecoder/SlaveAddressDecoder.vhd
    • Entity: SlaveAddressDecoder
    • Status: This is done as many processes. It could be simplified to a few case statements.
    • Description: This decodes the address signals for writes from the host to the ODR registers.

  • Write Pointer Duplicator
    • File: Stage1/WritePointerDuplicator/WritePointerDuplicator.vhd
    • Entity: WritePointerDuplicator
    • Status: Working
    • Description: To avoid the host driver having to read the write pointer of the DMADoneFIFO it is automatically written to a preset location in the host memory. The update is triggered by it changing, on the condition that it hasn't been updated within a set time.

  • Read Data Multiplexer
    • File: Stage1/ReadDataMux/ReadDataMuxQuad.vhd
    • Entity: ReadDataMUX
    • Status: Working. Other implementations have been tried, using BUFE and BUFT primitives but resulted in poorer performance. This method allows the data register to be migrated up the mux tree to achieve the required timing. If achieving the timing does become an issue in the future then an additional register stage can be added and the latency increased for that read (see PCIeInterface).
    • Description: This selects which register data is presented to the PCIe when a read is done.

  • Read Address Decoder
    • File: Stage1/ReadAddressDecoder/ReadAddressDecoderQuad.vhd
    • Entity: ReadAddressDecoder
    • Status:
    • Description: This controls the ReadDataMuxQuad . All data transfers from ODR to host are done using the DMAs. The decoding for each can be different. Host read operations are done by DMA0 with the Upper address bits used as Tags to indicate which BAR is doing the read, so that the correct decoding can be implemented.

  • Eth2X
    • File:
    • Entity:
    • Status:
    • Description:

  • Data Generator
    • File: Stage1/DataGenerator/DataGenerator.vhd
    • Entity: DataGenerator
    • Status:
    • Description: The data generator creates dummy packets of data so that testing can be done without the front end connected. The maximum data rate is 500MB/s (per channel). Xoff is implemented during the data part of the packet to stop FIFOs being over-run. The Xoff needs to be asserted before the FIFO is full to allow space to absorb the header (If the xoff occurs during the header).

  • Data Stream Multiplexer
    • File: Stage1/DataStreamMux/DataStreamMux.vhd
    • Entity: DataStreamMux
    • Status:
    • Description: The Data Stream Multiplexer is used to switch between the alternative front end data sources. The Ethernet interface and the data generator.

  • FIFO Duplicator
    • File: Stage1/FIFODuplicator/FIFODuplicator.vhd
    • Entity: FIFODuplicator
    • Status:
    • Description: The FIFO Duplicator makes a copy of a FIFO in host memory using DMA. This is so that reads across the PCIe bus become unnecessary. There are some parameters which can be configured to influence the performance. So that the bus is used efficiently the transfers can be held off until the fill of the FIFO is above a certain level. There is also a timeout so that if the FIFO isn't filled above the threshold data doesn't get left in the FIFO and not transferred to the host memory

  • DMA Write Address Decoder
    • File: Stage1/DMAWriteAddressDecoder/DMAWriteAddressDecoder.vhd
    • Entity: DMAWriteAddressDecoder
    • Status:
    • Description: There are very few writes done by DMA on the ODR. DMA is used to write data to the ethernet TX

  • DMA Read Enable Decoder
    • File: Stage1/DMAReadEnableDecoder/DMAReadEnableDecoder.vhd
    • Entity: DMAReadEnableDecoder
    • Status:
    • Description: The transfer of data for all reads is done by a DMA. Read from some registers, in particular FIFOs, require the register to update when the read has been completed. this is done with a read enable signal. Most registers do not need a read enable signal as the data only needs to be sampled.

  • DMA Queue
    • File: Stage1/DMAQueue/DMAQueue.vhd
    • Entity: DMAQueue
    • Status: Currently not used
    • Description: The DMA Queue allows multiple DMA descriptor to be put in a queue. As soon as one DMA is complete the next one in the queue will be loaded and started.

  • Eight to Thirty two bit width converter
    • File: Stage1/EightToThirtyTwo/EightToThirtyTwo.vhd
    • Entity: EightToThirtyTwo
    • Status:
    • Description: This receives 8 bit data from the Ethernet interface and converts it to 32 bit data. The start of the data packet will always be alligned on the lowest byte of the (32 bit) word. If the packet doesn't end on a 32 bit boundary the other bytes of the word will be filled with 0's. So that the exact length of the packet can be calculated the EndsOn marker indicates which byte the packet ended on.

  • Access counter
    • File: Stage1/AccessCounter/AccessCounter.vhd
    • Entity: AccessCounter
    • Status:
    • Description: The access counter is a debugging entity which allow counts to registers to be counted. Most registers don't care if the are accessed more times than expected but FIFOs will lose data if unexpectedly read. This can happen if a system converts a 64 bit read to two 32 bit reads.

  • FIFO Unpacker
    • File: Stage1/FIFOUnpacker/FIFOUnpacker.vhd
    • Entity: FIFOUnpacker
    • Status: In Use
    • Description: The FIFO Unpacker takes the data from the Used Page FIFO and rearranges it into a wider format so that all bits are available at once. This will be replaced if a wider Used Page FIFO is implemented.

  • A Single data stream channel
    • File: Stage1/OneChannel/OneChannel.vhd
    • Entity: OneChannel
    • Status: in use
    • Description: A number of lower level components are unified in this entity to create an entity which can be used to generate any number of channels.

  • Global Control Register
    • File: Stage1/GlobalControlRegister/GlobalControlRegister.vhd
    • Entity: GlobalControlRegister
    • Status: In use
    • Description: The global control register allows the host to control various parts of the ODR. This is mainly used to allow individual parts of the ODR to be reset or held reset. The power on reset propagates through here

  • Used FIFO Arbitration
    • FILE: Stage1/UsedFIFOArb/UsedFIFOArb.vhd
    • Entity: UsedFIFOArb
    • Status: The code will need some modification to fully support the number of channels generic.
    • Description: The Used FIFO arbitration brings together the Used FIFOs of the 4 channel to a single interface. The channel selected by the arbiter is presented to the downstream interface. The arbitration is done as a round-robin of the Used FIFOs which have data.

  • Primary DMA Control
    • File: Stage1/PrimaryDMAControl/PrimaryDMAControl.vhd
    • Entity: PrimaryDMAControl
    • Status: Working
    • Description: The Primary DMA Control sets up a DMA of the PCIe core. It transfers the data from the buffer memory to the host memory. The Free Page FIFO provides the address of the next free page of memory in the host system. Information about the packet in the buffer memory is read from the Used FIFO (via the Used FIFO Arbitration). Each packet in the buffer memory is transferred to a separate page in the host memory. On completion of the DMA some information is written to the DMA done FIFO giving a summary of the transfer.


-- BarryGreen - 05 Jun 2007

-- BarryGreen - 29-Mar-2010

Edit | Attach | Watch | Print version | History: r2 < r1 | Backlinks | Raw View | WYSIWYG | More topic actions
Topic revision: r2 - 2010-03-29 - PeterJones
 
    • Cern Search Icon Cern Search
    • TWiki Search Icon TWiki Search
    • Google Search Icon Google Search

    CALICE All webs login

This site is powered by the TWiki collaboration platform Powered by PerlCopyright & 2008-2020 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback