Verification of v5.2.1 firmware and software release
Details
Date |
02/11/2020 |
Location |
University of Bristol lab |
People |
Stoyan Trilov |
Test objective
Verify the operation of the software and firmware following the fixing of several bugfixes, and the addition of a new output port in endpoint firmware block.
The bugs fixed are documented below:
Delay adjustment:
https://gitlab.cern.ch/protoDUNE-SP-DAQ/timing-board-firmware/-/issues/4
Buffer reset:
https://gitlab.cern.ch/protoDUNE-SP-DAQ/timing-board-firmware/-/issues/1
Test setup
Hardware
An AIDA 2020 TLU was configured to acts as master using the overlord fw design. An Enclustra AX3+PM3 with a timing FMC (pc053a) acted as an endpoint. The output from the TLU was fed into an 1:8 passive optical splitter via single mode optical fibre. The timing FMC was connected to one of the splitter outputs using a single mode optical fibre.
TLU UID: 0x5410ecbba408
FMC UID: 0xd880395e1a6a
Firmware
The bitfile used for the TLU was:
http://pdts-fw.web.cern.ch/pdts-fw/commits/6563557bc77e4b3039602e03cb0d09fd76d876a6/pipeline2043668/overlord_tlu_master_runner-6bb6b053-project-19909-concurrent-2_201027_1144.tgz
.
The endpoint bitfile was generated using the dep file, timing-board-firmware/projects/endpoint/firmware/cfg/top_a35_ax3_pm3_pc053a.dep from
https://gitlab.cern.ch/protoDUNE-SP-DAQ/timing-board-firmware/-/commit/6563557bc77e4b3039602e03cb0d09fd76d876a6
. Synthesis, implementation and bitfile generation were done using Vivado 2019.2 and IPBus v1.8.
Software
The software version used for this test was:
https://gitlab.cern.ch/protoDUNE-SP-DAQ/timing-board-software/-/commit/7d90ef3317f6f8f28948789ea84a884ace7ffb28
.
Device configuration
The TLU was configured using the following commands:
pdtbutler io PROD_MASTER reset
pdtbutler mst PROD_MASTER synctime
pdtbutler mst PROD_MASTER part 0 configure
The endpoint was configured using the commands below:
pdtbutler io EPT_0 reset --force-pll-cfg tests/etc/clock/devel/Si5344-PDTSCRT1NoZdm-RevD-400HzBW-Registers.txt
pdtbutler ept EPT_0 0 enable -a 0x1
pdtbutler ept EPT_0 0 status
Test results
Following the configuration of the TLU and timing partition 0, the partition status command,
pdtbutler mst PROD_MASTER part 0 status
yielded the following output:
Created device PROD_MASTER
ID: design 'overlord' on board 'tlu' on carrier 'enclustra-a35'
Master FW rev: 0x50100, partitions: 4, channels: 5
-- Master state---
=> Cmd generator counters
----------------------------------------------------------------------------
| | Accept counters | Reject counters |
----------------------------------------------------------------------------
| Chan | cnts | hex | cnts | hex |
----------------------------------------------------------------------------
| 0x0 | 0 | 0x0 | 0 | 0x0 |
| 0x1 | 0 | 0x0 | 0 | 0x0 |
| 0x2 | 0 | 0x0 | 0 | 0x0 |
| 0x3 | 0 | 0x0 | 0 | 0x0 |
| 0x4 | 0 | 0x0 | 0 | 0x0 |
----------------------------------------------------------------------------
=> Partition 0
Control Status registers
+---------------+------+ +----------+-----+
| buf_en | 0x0 | | buf_err | 0x0 |
| frag_mask | 0x0 | | buf_warn | 0x0 |
| part_en | 0x1 | | in_run | 0x0 |
| rate_ctrl_en | 0x1 | | in_spill | 0x0 |
| run_req | 0x0 | | part_up | 0x1 |
| spill_gate_en | 0x1 | | run_int | 0x0 |
| trig_ctr_rst | 0x0 | +----------+-----+
| trig_en | 0x0 |
| trig_mask | 0xf1 |
+---------------+------+
Timestamp: 0x11cfbef9ca60b4a -> Mon, 02 Nov 2020 11:53:18 +0000
EventCounter: 0
Buffer status: OK
Buffer occupancy: 0
----------------------------------------------------------------------------
| | Accept counters | Reject counters |
----------------------------------------------------------------------------
| Cmd | cnts | hex | cnts | hex |
----------------------------------------------------------------------------
| TimeSync | 207 | 0xcf | 0 | 0x0 |
| Echo | 0 | 0x0 | 0 | 0x0 |
| SpillStart | 0 | 0x0 | 0 | 0x0 |
| SpillStop | 0 | 0x0 | 0 | 0x0 |
| RunStart | 0 | 0x0 | 0 | 0x0 |
| RunStop | 0 | 0x0 | 0 | 0x0 |
| WibCalib | 0 | 0x0 | 0 | 0x0 |
| SSPCalib | 0 | 0x0 | 0 | 0x0 |
| FakeTrig0 | 0 | 0x0 | 0 | 0x0 |
| FakeTrig1 | 0 | 0x0 | 0 | 0x0 |
| FakeTrig2 | 0 | 0x0 | 0 | 0x0 |
| FakeTrig3 | 0 | 0x0 | 0 | 0x0 |
| BeamTrig | 0 | 0x0 | 0 | 0x0 |
| NoBeamTrig | 0 | 0x0 | 0 | 0x0 |
| ExtFakeTrig | 0 | 0x0 | 0 | 0x0 |
| 0xf | 0 | 0x0 | 0 | 0x0 |
----------------------------------------------------------------------------
The endpoint status command
pdtbutler ept EPT_0 0 status
gives the output below.
Created endpoint device EPT_0
+---------+
| 0 |
| 0x50100 |
+---------+
+------------------+--------------------------------------------+
| Endpoint | 0 |
+------------------+--------------------------------------------+
| State | Waiting for phase adjustment command (0x6) |
| Partition | 0 |
| Address | 1 |
| Timestamp | Mon, 02 Nov 2020 11:56:14 +0000 |
| Timestamp (hex) | 0x11cfbf1a92d5ed8 |
| EventCounter | 0 |
| Buffer status | OK |
| Buffer occupancy | 0 |
+------------------+--------------------------------------------+
--- Endpoint state ---
+------------+----------+
| Endpoint | 0 |
+------------+----------+
| buf_err | 0x0 |
| buf_warn | 0x0 |
| cdelay | 0x0 |
| ep_rdy | 0x0 |
| ep_rsto | 0x1 |
| ep_stat | 0x6 |
| fdelay | 0x0 |
| in_run | 0x0 |
| in_spill | 0x0 |
| sfp_tx_dis | 0x1 |
+------------+----------+
--- Command counters ---
+--------------+----------+
| Endpoint | 0 |
+--------------+----------+
| TimeSync | 32 |
| Echo | |
| SpillStart | |
| SpillStop | |
| RunStart | |
| RunStop | |
| WibCalib | |
| SSPCalib | |
| FakeTrig0 | |
| FakeTrig1 | |
| FakeTrig2 | |
| FakeTrig3 | |
| BeamTrig | |
| NoBeamTrig | |
| ExtFakeTrig | |
| None | |
+--------------+----------+
Delay adjustment
Sending the delay adjustment command,
pdtbutler mst PROD_MASTER align apply-delay 0x1 0x3 0x7 --force
applies a coarse delay of 0x3, and a fine delay of 0x7 to endpoint address 0x1. The endpoint status after delay adjustment is:
Created endpoint device EPT_0
+---------+
| 0 |
| 0x50100 |
+---------+
+------------------+---------------------------------+
| Endpoint | 0 |
+------------------+---------------------------------+
| State | Ready (0x8) |
| Partition | 0 |
| Address | 1 |
| Timestamp | Mon, 02 Nov 2020 11:57:47 +0000 |
| Timestamp (hex) | 0x11cfbf2bc97f2b3 |
| EventCounter | 0 |
| Buffer status | OK |
| Buffer occupancy | 0 |
+------------------+---------------------------------+
--- Endpoint state ---
+------------+----------+
| Endpoint | 0 |
+------------+----------+
| buf_err | 0x0 |
| buf_warn | 0x0 |
| cdelay | 0x3 |
| ep_rdy | 0x1 |
| ep_rsto | 0x0 |
| ep_stat | 0x8 |
| fdelay | 0x7 |
| in_run | 0x0 |
| in_spill | 0x0 |
| sfp_tx_dis | 0x1 |
+------------+----------+
--- Command counters ---
+--------------+----------+
| Endpoint | 0 |
+--------------+----------+
| TimeSync | 124 |
| Echo | |
| SpillStart | |
| SpillStop | |
| RunStart | |
| RunStop | |
| WibCalib | |
| SSPCalib | |
| FakeTrig0 | |
| FakeTrig1 | |
| FakeTrig2 | |
| FakeTrig3 | |
| BeamTrig | |
| NoBeamTrig | |
| ExtFakeTrig | |
| None | |
+--------------+----------+
indicating the successful application of the coarse and fine delays. The following combinations of delay values were also verified.
cdel |
fdel |
0x0 |
0x0 |
0x0 |
0x1 |
0x1 |
0x0 |
Buffer reset error:
The functioning of the event buffer was verified by configuring a fake triggers generator, and enabling triggering for partition 0. The commands issued were:
pdtbutler mst PROD_MASTER faketrig-conf 0 1
pdtbutler mst PROD_MASTER part 0 configure --no-spill-gate
pdtbutler mst PROD_MASTER part 0 start
pdtbutler mst PROD_MASTER part 0 trig
The presence of events in the buffer was verified by the status command (output below).
Created device PROD_MASTER
ID: design 'overlord' on board 'tlu' on carrier 'enclustra-a35'
Master FW rev: 0x50100, partitions: 4, channels: 5
-- Master state---
=> Cmd generator counters
----------------------------------------------------------------------------
| | Accept counters | Reject counters |
----------------------------------------------------------------------------
| Chan | cnts | hex | cnts | hex |
----------------------------------------------------------------------------
| 0x0 | 100 | 0x64 | 0 | 0x0 |
| 0x1 | 0 | 0x0 | 0 | 0x0 |
| 0x2 | 0 | 0x0 | 0 | 0x0 |
| 0x3 | 0 | 0x0 | 0 | 0x0 |
| 0x4 | 0 | 0x0 | 0 | 0x0 |
----------------------------------------------------------------------------
=> Partition 0
Control Status registers
+---------------+------+ +----------+-----+
| buf_en | 0x1 | | buf_err | 0x0 |
| frag_mask | 0x0 | | buf_warn | 0x0 |
| part_en | 0x1 | | in_run | 0x1 |
| rate_ctrl_en | 0x1 | | in_spill | 0x0 |
| run_req | 0x1 | | part_up | 0x1 |
| spill_gate_en | 0x0 | | run_int | 0x1 |
| trig_ctr_rst | 0x0 | +----------+-----+
| trig_en | 0x1 |
| trig_mask | 0xf1 |
+---------------+------+
Timestamp: 0x11cfc0f86722f2e -> Mon, 02 Nov 2020 12:38:59 +0000
EventCounter: 27
Buffer status: OK
Buffer occupancy: 162
----------------------------------------------------------------------------
| | Accept counters | Reject counters |
----------------------------------------------------------------------------
| Cmd | cnts | hex | cnts | hex |
----------------------------------------------------------------------------
| TimeSync | 50 | 0x32 | 0 | 0x0 |
| Echo | 0 | 0x0 | 0 | 0x0 |
| SpillStart | 0 | 0x0 | 0 | 0x0 |
| SpillStop | 0 | 0x0 | 0 | 0x0 |
| RunStart | 1 | 0x1 | 0 | 0x0 |
| RunStop | 0 | 0x0 | 0 | 0x0 |
| WibCalib | 0 | 0x0 | 0 | 0x0 |
| SSPCalib | 0 | 0x0 | 0 | 0x0 |
| FakeTrig0 | 27 | 0x1b | 4 | 0x4 |
| FakeTrig1 | 0 | 0x0 | 0 | 0x0 |
| FakeTrig2 | 0 | 0x0 | 0 | 0x0 |
| FakeTrig3 | 0 | 0x0 | 0 | 0x0 |
| BeamTrig | 0 | 0x0 | 0 | 0x0 |
| NoBeamTrig | 0 | 0x0 | 0 | 0x0 |
| ExtFakeTrig | 0 | 0x0 | 0 | 0x0 |
| 0xf | 0 | 0x0 | 0 | 0x0 |
----------------------------------------------------------------------------
The output above indicates the event buffer does not go into error state following a reset, and is able to store events.
--
StoyanMiroslavovTrilov - 2020-11-02