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-- UmutKose - 2017-03-09

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Introduction

Fluka Simulations

Proposed layout of the CRT Top Unit

The top unit of the tagger will be placed in the volume immediately below the concrete shielding plug. The largest space to be covered under the concrete plug is 27.1 × 11.2 m2. The allowed vertical space is about 30 cm. A set of IPE140 beams will span across the 11.2 m of lateral opening of the pit. In total 28 beams will cover the entire surface with a distance of about 1 m adjustable. Two beams support 6 modules therefore ~1 ton of weight is distributed over the opening. The inclined modules located in the left, right and back side will be brought down by help of crane and put on the moveable structure as shown below. Then the structure will be inclined to its final location and lock with help of steel rope (Figure 2). The modules in the front side will be supported by two 11.2 m long IPE140 beams (the structure shown in red in Figure 1).

* Figure 1: Support structures and modules in the experimental hall



* Figure 2: Support structure for the inclined modules. Each module will be brought by crane down and put on the moveable structure. Then using the middle hook on the structure, it will be inclined to its position by crane and fixed by steel rope.

The idea is to install independent square modules placed each one contiguous to the next one. Each module contains both X and Y oriented scintillator bars. the entire surface below the concrete plug will be covered by 84 modules of dimension 1.86 × 1.86 m2, leaving a minimal space on the sides for services. Additional 38 modules will be inclined at about 30 degreed to assemble the sloping parts of the top CRT unit. Including 3% of spare modules, we will need about 125 modules in total. The non active area between contiguous modules will be kept minimal and below 1% of the entire surface. Each module is equipped with its own light readout system and the front-end electronics. The connectivity requirements are kept minimal.

* Figure 3: Top CRT system with its support structure and T600 detector.

CRT module design

First Design:

Each module will be placed inside an Al box of external dimension of 186×186 cm2 . Aluminium U-profile 1 mm thick will close laterally the box and reinforced by adding 3 pieces of U-profile below. The top aluminium plate will be 0.5 mm thick, the lower one 2 mm and will support the box on the rail system,

* Figure 4: CRT Module first design: A single XY-module made of two layers of eight scintillator bars within the box.

Evaluation in the Design:

In the frist design we were planning to use U-frames for closing the module. And cables were planned to be collected between 1st layer of scintillator bars and bottom Aluminium plate. In order to avoid any damage to the cables and ease the assembly we changed the type of closing frame to the one shown below on the left. In this way we could use the channel for collecting the cables in one position and then plug into the PCB adapter. Further improvement on the assembly and module construction have been done by defining a new type of extruded aluminium frame to close the module. In this way upper and bottom parts of the module can be separated and easily assembled.

* Figure 5: Extruded frame to close the module:

* Figure 6: New CRT module Design:

Prototyping:

• PrototypingCRTModule_23March2017.pptx: CRT module prototyping

Scintillators

We have carried out several tests using PVT-based (polyvinyl toluene, BC 408), and polystyrene doped with different composition of pTP and POPOP: cast plastic scintillator samples and extruded scintillator samples.

* Figure 5: scintillator bar with fibers, grooves and connector:

Wavelength Shifting Fibers

The scintillation light is collected in 1.0 mm diameter Kuraray Y- 11(200)M wavelength-shifting fibers on the surface of the bars. Fibers are glued into the grooves in each scintillator barss. Gluing ensures stability of the connection between the fiber and the readout, and also improve the optical coupling between scintillator and fiber. The fibers are readout only from one end, the opposite end-side of the fibers is going to be mirrored in order to maximize the light yield from the far end of the bar. Mirroring procedures follows the technique developed for the fibers of the ATLAS HCAL: polishing the end of the fibers and then coating aluminium reflective layers of a few micron thickness by means of Al sputtering in a vacuum.

Silicon Photomultipliers

The SiPM has several advantages compared to the conventional photomultiplier tubes including high ruggedness, compactness (millimetres in size), low operating voltage requirements, long lifespan, lower costs, the ability to measure very weak light signals at the single photon level and immunity to electric and magnetic fields. And no light guides between the scintillator and the SiPM are necessary. The response of the SiPM to optical signals is influenced by many factors such as photon-detection efficiency, recovery time, gain, optical crosstalk, afterpulsing, dark count, and detector dead time.

Hamamatsu S13360-1350CS MPPC Silicon Photomultipliers (SiPM) has 1.3×1.3 mm2 active area made up of 667 pixels of 50 µm pitch, yielding a filling factor of 74%. It is used to convert wavelength shifted scintillation light to electrical pulses which carry timing information and have amplitudes proportional to the energies deposited. The breakdown voltage is about 53±5 V and the gain is at the level of 1.7 106 at 25 oC. SiPM has a temperature coefficient for the breakdown voltage. A typical temperature coefficient for the breakdown voltage for this device is of 50 mV/oC. The photon detection efficiency is about 40% at 450 nm wavelength. The dark count rate and cross talk is measured to be 84 kHz and 3%, respectively.

Front-end Boards

We are considering using of SBND front-end board (FEB) developed by the University of Bern. The board is commercialized and maintained by CAEN (with catalogue number of A1702 “32 channel silicon photomultiplier read out front-end-board”). Readout board unit provides induvidual SiPM bias voltage in the range of 40-90 Volts. A channel-by-channel input of 8-bit Digital-to-Analog Convertor (DAC) within a CITIROC 32-channel ASIC allows adjusting the SiPM voltage in the range of +0.5 to +4.5 Volts. That allows fine SiPM gain and dark noise adjustment at the system level in order to correct for the nonuniformity of SiPMs. The analog SiPM signal is processed by the CITIROC ASIC chip. First the signal for each individual channel is amplified by low noise charge preamplifier for further signal processing. Adjusting the gain of the preamplifier, a range of 1 – 2000 photoelectrons (assuming a SiPM gain of 106) can be measured. The amplified signal is then feed to a fast RC-CR shaper with a 15 ns peaking time followed by discriminator whose threshold is set by a common 10-bit DAC. Additionaly, 4-bit DAC is used for fine adjustment of discriminator threshold setting for each individual channel. When the signal is above the set threshold, a trigger is generated and sent to a Field Programmable Gate Array (FPGA). For each scintillator a coincidence between two channels (C0&C1, C2&C3, ….) is done by AND logic within FPGA. From the coincidence signal of all 16 paired channels, the logical OR is produced and the result considered as a primary event trigger in one layer of the module, (say X-Layer), as shown in Figure 13 lower panel. Within the FPGA, the signal also triggers the generation of a time stamp for the event (using two time reference pulses; external GPS time for global timing and accelerator beam spill pulse). The same flow also true for other layer of scintillator bars within the module. Primary event trigger produces and sends back a hold signal (kept active for at least 160 ns) to all 32 channels. In this period the circuit detects high level input which is produced from the other layer (say Y-layer) of scintillator samples the event is VALID. If no signal is received from the other layer during 150 ns, the event is discarded. Valid events will be digitized by 12 bits ADCs and saved to the FEB internal buffer with a capacity of 1024 events (each event 76 bytes long). FEB buffers are sent to a PC when requested, over a 1Gb ethernet interface. Data communication with FEBs is always initiated by the host PC via daisy chained CAT-5 twisted pair Ethernet cables connected to a single Ethernet port of the PC. Time reference signals to the FEB are provided with 3 mm diameter coaxial cables.