HSTD11 & SOIPIX2017

Abstracts

Silicon pixel-detector R&D for CLIC

  • Speaker: Dominik Dannheim (CERN)
  • Status: Accepted for oral presentation
  • Abstract: The physics aims at the proposed future CLIC high-energy linear e+e- collider pose challenging demands on the performance of the detector system. In particular the vertex and tracking detectors have to combine precision measurements with robustness against the expected high rates of beam-induced backgrounds. The principal challenges are: a point resolution of a few μm, ultra-low mass (~0.2% X0 per layer for the vertex region and ~1% X0 per layer for the outer tracker), very low power dissipation (compatible with air-flow cooling in the inner vertex region) and pulsed power operation, complemented with ~10 ns time stamping capabilities. A highly granular all-silicon vertex and tracking detector system is under development, following an integrated approach addressing simultaneously the physics requirements and engineering constraints. For the vertex-detector region, hybrid pixel detectors with small pitch (25 μm) and analog readout are explored. For the outer tracking region, fully integrated CMOS sensors with high-resistivity substrate are under consideration (HR-CMOS, SOI). Prototypes of readout ASICs implemented in 65 nm CMOS technology with 25 μm pixel pitch have been produced (CLICpix and CLICpix2). Hybridisation concepts have been developed for interconnecting these chips either through capacitive coupling to active High-Voltage-CMOS sensors (CCPDv3 and C3PD) or through bump-bonding to ultra-thin planar active-edge sensors. Recent R&D achievements include results from beam tests with various hybrid assemblies as well as with technology prototypes of integrated CMOS sensors. Simulations based on Geant4 and TCAD are used to validate the experimental results and to assess and optimise the performance of various detector designs. The R&D project also includes the development of through-silicon via (TSV) technology, as well as various engineering studies involving thin mechanical structures and full-scale air-cooling tests. An overview of the R&D program for silicon detectors at CLIC will be presented.
  • Slides

Beam test results of a monolithic pixel detector designed in SOI 200nm technology

  • Speaker: Szymon Bugiel (AGH Krakow)
  • Status: Accepted for oral presentation
  • Abstract: For tracking detectors at future linear colliders a high-precision position measurement is required. In order to limit multiple scattering, a detector with low material budget id advantageous. Monolithic structures represent a promising solution for such detectors. This work presents the test beam results of pixel detectors fabricated in Lapis $200~nm$ Silicon-On-Insulator (SOI) CMOS technology. The SOI prototypes were tested in Summer 2017 - at CERN's SPS H6 beam line with 120 GeV pion beams using a Timepix3 telescope as a reference. Two wafer types with different resistivity and detector thickness were tested: Floating Zone type n and Double SOI type p. Moreover, the measured matrix consists of two different pixel types, one based on charge preamplifier architecture and one based on source-followers. The data was analysed in terms of spatial resolution and detector efficiency. The analysis chain included pedestal and noise calculation, different cluster reconstruction algorithms, as well as alignment and eta correction. The preliminary results give a resolution of about 2.5 $\mu m$ for 30 $\mu m$ square pixel pitch.
  • Slides

The general performance of source-follower and charge-preamplifier SOI pixel detectors

  • Speaker: Roma Bugiel (AGH Krakow)
  • Status: Accepted as poster presentation
  • Abstract: The SOI CMOS technology allows to fabricate monolithic pixel detectors in which the readout electronic and the sensor matrix are integrated on the same wafer. Characterization of a device designed in Cracow and produced in Lapis 0.2 ?m Fully-Depleted, Low-Leakage SOI CMOS technology was performed. The tested matrix consists of two pixel types: source-follower and charge-preamplifier architecture. In addition, the charge preamplifiers are designed with two different sensor layouts. The whole matrix comprises an area of 16 36 squared pixels of 30 micron pitch. The detector is read out in rolling shutter mode. In this presentation, the performance and measurement results of the prototypes produced on high resistivity floating zone (FZ-n) and novel Double SOI wafers are presented. Using Am241 and Fe55 radioactive sources the detector calibration was done and the noise was measured, giving the ENC (Equivalent Noise Charge) of about 100 e?. In addition, the leakage currents were measured showing several pA per pixel for FZ(n) and almost zero (below 0.1 pA) for Double SOI.
  • Poster
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PDFpdf 2017_HSTD11_SzymonBugiel.pdf r1 manage 1577.5 K 2018-01-30 - 11:50 EvaSicking  
PDFpdf CLIC-SiPixelRD_HSTD11_11Dec2017.pdf r1 manage 9808.8 K 2018-01-30 - 11:50 EvaSicking  
PDFpdf Roma_Bugiel_HSTD_poster_f.pdf r1 manage 1347.3 K 2018-01-30 - 11:50 EvaSicking  
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