Pixel 2018


Results from test-beam measurements of monolithic pixel detectors in SOI technology

  • Speaker: Roma Bugiel, Marek Idzik
  • Status: Accepted
  • Time: (20 + 5) min
  • Abstract: Tracking and vertex detectors at future linear colliders such as CLIC require a high-precision position measurement. A single-point spatial resolution of about 3 microns is foreseen for the CLIC vertex detector. In order to achieve this goal, detectors with low material budget and small pitch have to be developed. One solution for this are monolithic pixel structures. These do not require bump-bonding of individual sensor and read-out ASICs, which leads to an overall lower material budget with reduced multiple scattering and improved spatial resolution. The Silicon-On-Insulator CMOS is one of the modern silicon technologies that allows to fabricate the monolithic pixel structures in which the readout electronics and the sensor matrix are integrated on the same wafer. In this talk, the test-beam data analysis results of Lapis 200nm SOI pixel detectors are presented. The SOI detectors were designed in AGH-UST in Cracow and tested at the CERN SPS H6 beam line in 2017. The presented detectors were fabricated on two different wafers type: FZ(n) and Double SOI(p), with thicknesses of 500 um and 300 um respectively. The pixel size was 30x30 um. The tested matrix consisted of two pixel types: source-follower and charge-preamplifier architecture. The data analyses focused on spatial resolution and efficiency estimation. A novel procedure of eta-correction for multi-pixel clusters was introduced. Moreover, the influence of various clusterization methods on single-point resolution was studied. Finally, single-point resolutions below 2.4 um for the FZ(n) wafer and 3.5 um for the DSOI(p) was achieved. A high detector efficiency of about 98% was measured. Such performance shows that the tested structures are promising prototypes, fulfilling the condition for spatial resolution, for the CLIC vertex and tracking detectors.
  • Slides

Pixel-detector R&D for CLIC

  • Speaker: Mathieu Benoit (University of Geneva)
  • Status: Accepted
  • Time: (20 + 5) min
  • Abstract: The physics aims at the proposed future CLIC high-energy linear e+e- collider pose challenging demands on the performance of the detector system. In particular the vertex and tracking detectors have to combine precision measurements with robustness against the expected high rates of beam-induced backgrounds. A spatial resolution of a few microns and a material budget down to 0.2% of a radiation length per vertex-detector layer have to be achieved together with a few nanoseconds time stamping accuracy. These requirements are addressed with innovative technologies in an ambitious detector R&D programme, comprising hardware developments as well as detailed device and Monte Carlo simulations based on TCAD, Geant4 and Allpix-Squared. Various fine pitch hybrid silicon pixel detector technologies are under investigation for the CLIC vertex detector. The CLICpix and CLICpix2 readout ASICs with 25 micron pixel pitch have been produced in a 65 nm commercial CMOS process and bump-bonded to planar active edge sensors as well as capacitively coupled to High-Voltage (HV) CMOS sensors. Monolithic silicon tracking detectors are foreseen for the large surface (~140 square meters) CLIC tracker. Fully monolithic prototypes are currently under development in High-Resistivity (HR) CMOS, HV-CMOS and Silicon on Insulator (SOI) technologies. The laboratory and beam tests of all recent prototypes profit from the development of the CaRIBou universal readout system. This talk presents an overview of the CLIC pixel-detector R&D programme, focussing on recent test-beam and simulation results.
  • Slides

Simulations of CMOS sensors with a small collection electrode improved for a faster charge-collection and increased radiation tolerance

  • Speaker: Magdalena Munker (CERN)
  • Status: Accepted
  • Time: (20 + 5) min
  • Abstract: CMOS sensors with a small collection electrode are attractive for a wide range of applications due to the very low sensor capacitance allowing for a very low noise and analogue power consumption. Such sensors have been studied and developed for the ALICE ITS upgrade, where they have been selected as the technology of choice. To achieve a full lateral depletion in the sensor, a process modification has been performed, making this technology also attractive for detectors in harsh radiation environments, such as for the ATLAS ITk upgrade, and for detectors with time resolution requirements in the order of a few nanoseconds, such as the CLIC tracking system. However, the electric field in the sensor reaches a minimum in the pixel corners, more pronounced for larger pixel sizes, increasing the charge-collection time. This can result in a degraded timing resolution and loss of efficiency after irradiation. Recent studies of this technology have shown the challenge to achieve a fully efficient operation after irradiation and a timing resolution in the order of a few nanoseconds precision for pixel sizes of larger than approximately 40 micrometres. This paper presents three-dimensional self-consistent Technology Computer Aided Design Simulations for two concepts to improve the timing resolution and radiation hardness for a given pixel size: a mask change and an additional implant. The transient simulation has been performed for several variations of the proposed designs and of the operation conditions for non-irradiated and irradiated sensors. The simulation results indicate a significant decrease of the charge-collection time before and after irradiation and of the collected charge after irradiation. The new designs are now implemented in a next submission of the ATLAS prototype chips in this technology.
  • Slides

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