TWEPP2019

Abstracts

CLICTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker

• Speakers: Iraklis Kremastiotis (KIT)
• Status: Accepted as parallel talk
• Abstract:

The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a 180nm HR-CMOS Imaging Process. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of 16×128 detector channels, each measuring 300×30μm2. To ensure prompt charge collection, each channel is segmented in eight collection diodes, each containing a separate analog front-end. A simultaneous time and energy measurement is performed in the on-channel digital logic. Simulations show a minimum detectable charge of 93e− for 210mW/cm2 (continuous operation). The main design aspects, as well as the first results from laboratory measurements are presented. Summary

A novel monolithic pixel sensor chip, the CLIC Tracker Detector (CLICTD) chip, is presented. The chip was designed according to the requirements for the silicon tracker at the future Compact Linear Collider (CLIC). These requirements include an 8-bit Time of Arrival (ToA) measurement with 10ns time bins and a 5-bit Time over Threshold (ToT) measurement for time walk correction and precise hit spatial allocation. Other requirements involve a single point resolution of 7um along the transverse plane, a total material budget of 1-1.5% X0 per detection layer (allowing for ~200um for the silicon layers) and an average power consumption below 150mW/cm^2. Taking advantage of the low duty cycle of the CLIC beam, the analog front-end can be set to a standby power mode between bunch trains to minimise the average analog power consumption (power pulsing). The digital power consumption is minimised by means of clock gating. The resulting average power consumption over the CLIC cycle is 5mW/cm^2 for the matrix, plus 70mW for the periphery (for 3% occupancy).

The design was implemented in a 180nm High-Resistivity (HR) CMOS imaging process, where a deep P-well is used in order to shield the on-channel electronics from the collection electrode [1]. The signal is collected with a small N-well on the P-type high resistivity epitaxial layer. The small detector capacitance helps to minimise the analog power consumption and the noise in the front-end. The epitaxial layer is fully depleted by including an additional deep N-type implant. Using a process split, additional wafers are produced with a segmented deep N-type implant to increase the lateral field and thereby to reduce the charge collection time.

The CLICTD matrix comprises 16x128 detecting cells of 300x30um^2. Each cell is segmented in eight collection diodes each read out by its own Charge Sensitive Amplifier (CSA) to ensure prompt charge collection. The diodes are therefore spaced by 37.5um along the long direction. Every front-end includes a CSA, a discriminator and a 3-bit local threshold tuning DAC. Simulations show a minimum detectable charge of 93e-, an in-time charge of 720e- (where the time walk remains below 10ns) for 210mW/cm^2 (continuous operation, without power pulsing). Binary hit information is stored for each diode, while the simultaneous 8-bit ToA and 5-bit ToT measurement is performed in the on-channel digital logic for the combined output (by means of an "OR" gate) of all eight discriminator outputs.

The slow control is based on the I2C protocol, while a serial readout at 40 MHz, with a zero suppression algorithm, is employed. The chip was verified using the Universal Verification Methodology (UVM).

Along with the main design aspects, the first laboratory measurement results with the CLICTD chip will be presented. Measurement results will include a scan of the sensor I-V characteristics, DAC scans and a test of the slow control and readout logic. In addition, the first results on the pixel performance, using internal test pulses as well as a radiation source, will be presented.

[1] W. Snoeys et al., NIMA 871 (2017) 90-96

• Slides

CaRIBOu – A versatile data acquisition system based on programmable hardware

• Speakers:Tomas Vanat (CERN)
• Status: Accepted as poster
• Abstract:

CaRIBOu is a flexible data acquisition system for prototyping silicon pixel detectors. The core of the system consists of the Control and Readout (CaR) board, a versatile module providing the hardware environment for various target ASICs, including powering and slow-control infrastructure and high-speed full-duplex GTx links up to 12.5 Gbps. The CaR board connects to a Zynq system-on-chip board, which runs a fully featured Yocto-based Linux and a data acquisition framework (Peary). Using the CaRIBOu system significantly reduces the time required to test and debug detector prototypes by providing ready-to-use peripheries and re-useable software interfaces for a variety of detectors. Summary

Developing new detectors requires the design of an adequate readout and control system. Such a system typically consist of hardware in form of a readout board containing programmable logic to provide an interface to the chip, power supplies for biasing the detector chip, as well as DACs and ADCs for setting and measuring operation parameters, generating test pulses, etc. One also needs to write software for controlling the detector and hardware peripherals and for data readout. This process needs to be repeated for each new chip developed, which requires different voltage levels or different number of data lines. The CaRIBOu system, on the other hand, provides a robust, versatile DAQ system, which can be easily adjusted to the needs of different detectors. Using such a system therefore saves development cost and reduces the time needed to get first data from the detector. CaRIBOu is a combination of hardware and software modules that forms a stand-alone readout and DAQ system for detector prototypes. It was initially developed for testing newly developed pixel-detector chips for ATLAS and for a future CLIC detector. Adding support for a new chip is a matter of writing a piece of code performing an interface between the chip-specific features and the standard data and control interface of the CaRIBOu system. The system is based on a Xilinx Zynq System-on-Chip (SoC) architecture combining the power of a programmable hardware (FPGA) and a full Linux operating system allowing to run software in a high-level programming language. It can run either stand-alone, storing data to a local filesystem, or connected via network interface to a data storage or a superior control system. The data decoding and analysis can be done either directly in the system both in software and in FPGA-based hardware, or the data can be stored in a raw format and analysed offline. The talk presents the structure and capabilities of the DAQ system and shows example applications and future plans.

• Poster