Installation

After installing each HVCMOS-CLICpix assembly, there are a few steps which must be carried out

• The CLICpix should be equalised
• A threshold scan should be taken
• The operating threshold should be set

Equalisation and threshold scan

The default settings of the script clicpix_eqalize.py (found in /home/vertextb/uASIC/DAQ/software) are sufficient for equalising and performing the threshold scan. The clock is set to 20 MHz, with an Ikrum of 25 and shutter length of 1 ms during the threshold scan. The script is run after sourcing the environmental script env.sh, using the command

./clicpix_eqalize.py -e -s -n

The output of the equalisation is written to

/home/vertextb/uASIC/DAQ/software/data/DEVICE/equalization/DATE_TIME

This folder will contain a useful file called clicpix.cpc which contains the "baseline_mean" - the THL value where the noise sits - and the output of the threshold scan. The threshold of the clicpix is relative to the noise position and each THL step corresponds to roughly 10 electrons - therefore to set a threshold of 1000 electrons, THL should be set to a value 100 lower than the noise value.

To choose the operating threshold, run the script /home/dhynds/tbcode/macros/threscholdScanPlot.C from inside the root interpreter, after updating the path for the input file. In general for these devices we want to run at as low a threshold as possible, with the default around 1200 electrons. From the plot, check that the number of noisy pixels at this value of THL (120 steps below the noise) is less than ~100, otherwise use a lower value of THL. An example plot is attached below, zoomed into the region around the default THL for this device of 1100.

Once this is done the eudaq configuration file (CLICpix_testbeam_0515.conf) should be updated to point to the device equalisation, along with the default threshold values and scan ranges.

Checklist for change of CLICpix+CCPDv3 sample

• Kill CLICpix producer if still running.
• Turn off Keithley HV power that goes to CCPDv3.
• Turn off CLICpix FPGA board (switch on the board).
• Move upstream telescope arm further upstream until you can access the screws.
• Remove only the two screws for the chip board on the bottom side and slide it out downwards.
• Place the new chipboard and carefully insert the two screws again. Make sure to not them too hard into the nuts mounted on the backside, as those are only fixed by tape.
• Push back the upstream arm until the two capacitors sticking out slightly touch the tape on the adjacent telescope plane.
• Check distance between first and last telescope plane with ruler, to confirm that it is the same as measured previously (compare with corresponding elog entry).
• Switch back on Keithley HV power and CLICpix FPGA board.
• Equalise thresholds using standalone code (see above). Prepare configuration file.
• Test run 10k events with low intensity (Coll3 +-2, Coll8 +-2), beam-line scintillator 513 rate ~2E4 per spill.
  • Check ROI trigger acceptance and tune ROI if needed.
  • Check TOT distribution and tune CLICpix CLK divider setting if needed.
• Set back collimators to beam reference (currently Coll3 +-3, Coll8 +-4). Check that rate in beam-line scintillator 513 is around 8E5 per spill.
• Start threshold scan.

-- DanielHynds - 2015-05-12 -- DominikDannheim - 2015-05-17