TIPP2017

Abstracts

A multi-chip data acquisition system based on a heterogeneous system-on-chip platform

• Speaker: Adrian Fiergolski (CERN)
• Status: Accepted (talk)
• Time: 15+3min
• Track: Front-end electronics and fast data transmission, Trigger and data acquisition systems
• Abstract: The development of pixel detectors for future high-energy physics experiments requires flexible high-performance readout systems supporting a wide range of current and future device generations. The versatile readout system of the Control and Readout Inner tracking Board (CaRIBou) targets laboratory and high-rate test-beam measurements with a multitude of detector prototypes. Under the project umbrella, application-specific chipboards and a common interface card have been developed for a variety of pixel detector readout ASICs and active sensors. The boards are hosted by a commercial evaluation kit (ZC706). This talk focuses on the data acquisition system (DAQ) based on a heterogeneous Xilinx Zynq All Programmable System-on-Chip (AP SoC). The device integrates the software programmability of an ARM-based processor with the hardware programmability of an FPGA, enabling acceleration of the design, verification, test and commissioning processes. The CPU handles the slow control of the system, while the FPGA fabric performs data processing and data encapsulation in UDP datagrams moved by a Direct Memory Access (DMA) device through the High Performance Advanced Extensible Interface (AXI) port directly to the shared Random Access Memory (RAM). Further, data in RAM is accessed by the CPU for prompt analysis (data-quality monitoring, calibration, etc.) or is transferred eventually to a storage server over the Ethernet link using a standard Linux network stack and the DMA. Thanks to the fully capable dual-core processor running a Linux operating system, the DAQ board provides the unique user experience of a regular fully-functional remote terminal able to execute high level code (such as Python scripts). Moreover, as the code runs locally on the CPU integrated directly or indirectly (through the FPGA fabric) with the given ASIC, operations involving high input/output (I/O) activity (e.g. chip equalization) are not affected by network delays. The logic modules implemented in the FPGA fabric are available to the end user through the open source Linux device drivers maintained by the Xilinx community. In order to facilitate the creation of an embedded Linux distribution, CaRIBou provides a layer to the Yocto build framework supported by a large community of open-source and industrial developers. The talk presents the design of the SoC-based DAQ system, its building blocks and shows examples of the achieved functionality and performance for the CLICpix2 readout ASIC and the C3PD active CMOS sensor.
• Slides

A vertex and tracking detector system for CLIC

• Speaker: Andreas Matthias Nurnberg (CERN)
• Status: Accepted (Talk)
• Time: 15+3min
• Track: Experimental detector systems
• Abstract: The physics aims at the proposed future CLIC high-energy linear e+e- collider pose challenging demands on the performance of the detector system. In particular the vertex and tracking detectors have to combine precision measurements with robustness against the expected high rates of beam-induced backgrounds. The requirements include ultra-low mass, facilitated by power pulsing and air cooling in the vertex-detector region, small cell sizes and precision hit timing at the few-ns level. A detector concept meeting these requirements has been developed and an integrated R&D program addressing the challenges is progressing in the areas of ultra-thin sensors and readout ASICs, interconnect technology, mechanical integration and cooling. We present the proposed vertex and tracking detector system, its performance obtained from full-detector simulations, and give an overview of the ongoing technology R&D, including results from recent beam tests of prototypes.
• Slides

Integrated CMOS sensor technologies for the CLIC tracker

• Speaker: Ruth Magdalena Munker (CERN)
• Status: Accepted (talk)
• Time: 15+3min
• Track: Semiconductor detectors
• Abstract: The tracking detector at the proposed high-energy CLIC electron-positron collider will be based on small-pitch silicon pixel- or strip sensors arranged in a multi-layer barrel and end-cap geometry with a total surface of about 90 sqm. The requirements include single-point position resolutions of a few microns and time stamping with an accuracy of approximately 10 ns, combined with a low material budget of less than 2% of a radiation length per layer, including cables, cooling and supports. Mainly fully integrated CMOS sensors are under consideration. One of the candidate technologies is based on a 180 nm CMOS process with a high-resistivity substrate. Test beam measurements and TCAD simulations were performed for demonstrator chips consisting of an array of analog pixel matrices with different pixel pitch and a variety of collection-electrode geometries and process options. The analog signals of each matrix are read out by external sampling ADCs, allowing for a precise characterisation of the signal response. In this contribution we present the sensor design and show results from recent test-beam campaigns, as well as comparisons with TCAD simulations. The results show good spatial and timing resolution in line with the requirements for the CLIC tracker.
• Slides

Analysis and simulation of HV-CMOS assemblies for the CLIC vertex detector

• Speaker: Matthew Buckland (Liverpool University)
• Status: Accepted (talk)
• Time: 15+3min
• Track: Semiconductor detectors
• Abstract: The requirement of precision physics and the environment found in the proposed future high-energy linear e+e- collider, CLIC, result in challenging constraints for the vertex detector. In order to reach the performance goals, various sensor technologies are under consideration. Prototypes of an active pixel sensor with 25 μm pitch (CCPDv3) have been fabricated in a commercial 180 nm High-Voltage CMOS technology. The sensors are capacitively coupled to CLICpix readout ASICs with matching footprint, implemented in a commercial 65 nm CMOS process. Tests of the assemblies were carried out at the CERN SPS using 120 GeV pions over an angular range of 0°-80°. The measurements have shown an excellent tracking performance with an efficiency of >99% and a resolution of 5-7 μm over the angular range. These were then compared to simulations carried out using TCAD, showing a good agreement for the current-voltage, breakdown and charge collection properties. The simulations have also been used to optimise features for future sensor design.
• Slides

Detector challenges for future high-energy e+e- colliders

• Speaker: Eva Sicking (CERN)
• Status: invited
• Slides