Full Simulation Performance Monitoring

General infos

The responsible for the performance monitoring in 2012 is Gustavo Gil Da Silveira (Louvain).

Reports are based on the Performance Suite.

The purpose of this wiki is to report all anomalies observed in the monitoring of prereleases and production releases.

Prereleases

CMSSW_6_0_0_pre2 to _pre5

The following prereleases were checked on June 4th, 2012:

# CMSSW_6_0_0_pre5 >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_53_V4::All) >> slc5_amd64_gcc462
# CMSSW_6_0_0_pre4 >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_53_V4::All) >> slc5_amd64_gcc462
# CMSSW_6_0_0_pre3 >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_60_V0::All) >> slc5_amd64_gcc462
# CMSSW_6_0_0_pre2 >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_52_V9::All) >> slc5_amd64_gcc462

All prereleases

• All prereleases show all the events below the 2000MB limit.

VSIZE plot

• CMSSW_6_0_0_pre5: strange memory jump at the 50th event.
  • Rise of 150MB in virtual memory.
• CMSSW_6_0_0_pre4: larger oscillations than have been seen in previous other prereleases.

CPU TIME PER EVENT

• CMSSW_6_0_0_pre5: strange peak at 50th event

RSS plot

• CMSSW_6_0_0_pre5: same jump at the 50th event
  • all the anomalies seen in the 50th event should be somehow related.

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Releases

CMSSW_5_Y_Y

The following releases were checked on June 4th, 2012:

# CMSSW_5_3_1          >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_53_V5::All)   >> slc5_amd64_gcc462 
# CMSSW_5_3_0          >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_53_V4::All)   >> slc5_amd64_gcc462
# CMSSW_5_2_5_cand1    >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_52_V9::All)   >> slc5_amd64_gcc462
# CMSSW_5_2_5          >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_52_V9::All)   >> slc5_amd64_gcc462
# CMSSW_5_1_2          >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_50_V15A::All) >> slc5_amd64_gcc462
# CMSSW_5_1_1          >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_50_V13::All)  >> slc5_amd64_gcc462
# CMSSW_5_0_1          >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_50_V13::All)  >> slc5_amd64_gcc434
# CMSSW_5_0_0_g4emtest >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_50_V8::All)   >> slc5_amd64_gcc434
# CMSSW_5_0_0          >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_50_V8::All)   >> slc5_amd64_gcc434

All releases

• All prereleases show all the events below the 2000MB limit.

VSIZE plot

• CMSSW_5_2_5_cand1: smaller oscillations than have been seen in other releases.
  • it is using more virtual memory (increment of 150MB).
• CMSSW_5_0_1 AND 5_0_0_g4emtest: higher peaks in the plot #events vs VSIZE.
  • few events using more memory than in other releases.

CMSSW_4_4_Y

The following releases were checked on June 4th, 2012:

# CMSSW_4_4_3             >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_44_V7::All) >> slc5_amd64_gcc434
# CMSSW_4_4_2_patch10     >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_44_V7::All) >> slc5_amd64_gcc434
# CMSSW_4_4_2_p10JEmalloc >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_44_V7::All) >> slc5_amd64_gcc434
# CMSSW_4_4_1             >> TTBAR >> GEN,SIM,DIGI,L1,DIGI2RAW (RAWSIM, LowLumiPileUp, MC_44_V6::All) >> slc5_amd64_gcc434

All releases

• All prereleases show all the events below the 2000MB limit.

VSIZE plot

• CMSSW_4_4_2_p10JEmalloc: higher virtual memory at the 100th event -> 1760MB.
  • other releases have the 100th event around 1600MB.
• Smoother growing in virtual memory than other releases (smaller oscillations).

RSS plot

• CMSSW_4_4_2_p10JEmalloc: larger oscillations, which is not seen in other releases.

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Missing workflows

Evolution of CPU time and VMemory

The plots below show the evolutions of CPU time and VMemory among the CMSSW releases.

-- GustavoGilDaSilveira - 26-Jun-2012