The new (2014) DAQ software

The code

The code is committed in svn:

For example, you can check-out the head (= trunk) version with:

svn co svn+ssh:// MY_PATH

In both cases you need the dreamdaq password - that I will send you in a separate message. The user dreamdaq has also a lxplus account where everything is backed up.

I checked in and tagged in svn few running versions ... the last one being always the most up-to-date working one.

The DAQ part of the code is subdivided into few different subdirectories:

- scripts: bash shell scripts ... that could/should be a lot
simplified (or at least partially eliminated)

- VMElib: VME library for the hardware module access

- FIFOlib: library for the real-time sharing of data among the 4
data acquisition processes

- DaqControlInterface: the graphical user interface code

- top level directory: the main DAQ processes (myReadOut,
myDataWriter, sampler) and few utilities

Presently the DaqControlInterface just executes scripts that in turn control (i.e. start, stop and kill) the data handling processes. It would be good, I think, to bypass the scripts and implement a direct communication with the processes via some message passing protocol.

Rebuilding libraries and binaries

To rebuild daq libraries and binaries, I implemented a TOP makefile (MakeAllDreamDaq), that runs over all the sub-packages. I also defined a few functions in the .bashrc file (the machine is pcdreamus, user dreamtest):

1) ddq_clean -> make -f MakeAllDreamDaq clean
to clean up everything

2) ddq_headers -> make -f MakeAllDreamDaq headers
to install the headers in ~/include

3) ddq_make -> make -f MakeAllDreamDaq all
to rebuild binaries

4) ddq_install -> make -f MakeAllDreamDaq install
to install libraries and executables in ~/lib & ~/bin

5) ddq_fromscratch -> make -f MakeAllDreamDaq fromscratch
to do all the above in sequence 1, 2, 3, 4

So this is sufficient to rebuid everything:
cd DreamDaq

Trigger setting

At the twiki page: TriggerBox

you can find the .vhd and .ucf files needed to build the project (the .vhd files define the logic and the .ucf the I/O port mapping).

To reload the FPGA, you have to use the XILINX ISE platform (type the command "ise" to open it).

The present scheme is also saved at the same page:

while the connections to the DAQ modules are documented in:

Readout modules

First VME crate:

1) V2718 controller, connected to the second link on the PC board
2) V513 I/O register, mapped at 0xa00000
3) V1742 DRS4 module mapped at 0x0032000, connected to the third link
4) V976 fan-out module
5) V814 discriminator, mapped at 0xcc0000
6) Pavia adapter for the trigger board
7) V262 I/O register, mapped at 0x400000

Second VME crate:

1) V2718 controller, connected to the first link on the PC board
2) 4 V792 charge integrating ADCs, mapped at:
3) V862 charge integrating ADC, mapped at 0x03000000
4) V775 TDC, mapped at 0x08000000

Look at the attached file -- RobertoFerrari - 2014-12-07

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Topic revision: r2 - 2014-12-08 - MicheleCascella
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