Calo Electronic Setup for Herschel

This page intend to collect useful informations on how to use the CaloFE electronic setup for Herschel, the control software and the tests.

Description of the Test Bench hardware and software setup

A detailed description of the test bench setup located in 2885 2-0001, as well as of the main panel of the Calo dedicated ECS software (CAT) can be found at this page: SetupDescription

Hands-on CAT and the boards.

Some very simple simple operation to get familiar with CAT can be found at this page HandsOnCAT . Reading noise, writing RAM in the FE and reading them in the CROC, spying the TVB, those operation are requiered in almost all tests. It also allow to check the boards are functionnal.

WinCC

WinCC Herschel project is installed on vedev01 at the lab.

Tests

On this page CaloFETest are documented all tests done to validate the setup.

Use the clock division to fake L0 sequence at given rate

Using a generator

Sinusoidal

Arbitrary Waveform generator

Would that match: https://aismisc.cern.ch/aismisc/f?p=152:7:219375306878245::NO:RP,7:P7_ITEM:0408 to check if we could use it to see how the electronic behave to signal every 25ns, and one empty bunch, with waveform close to expected from PM. Check amplitude and frequency are ok. Do not plug or unplug cables from the outputs when the channel is turned on!

Running a timing scan

1. Set up the AWG:
  • Under settings tab:
    • Timing - internal clock source, external reference clock fixed to 20 MHz
    • Run mode - triggered
    • Trigger - level around -0.5V (check with the scope). Negative trigger from the CROC, so trigger on negative slope. 50 ohm input impedance
    • Channel 2 - this is the output we tend to use. The signal should be negative. A reasonable signal which is 15ns wide and 50mV high will give you an ADC count of order 1000. To set this up change amplitude to 0.050Vpp and offset to -0.025V.
  • Load signal using "File> Import from file"
  • Drag signal from waveform list to channel under study
2. Set up CAT
  • Make sure lbcalospecs01 is connected to the CROC
  • Start CAT
  • Load the HerschelTVB config file
  • Change Data Path to a sensible place to store the log file
  • Tick 'save log'
  • Change "Element" to CROC and choose TimingScan from the drop-down box below
  • Open the CROC panel and change clock input to "TTCRq OR CROC" as in standard setup routine, and validate this (buttons should change colour to green)
  • Start a timing scan by pressing "Start 1 event" (single arrow at top of main CAT panel). The timing scan code internally repeats 20 times - you don't need to take 20 events (and, in fact, telling CAT to try and take more than 1 event from the main panel doesn't work).
3. Analyse
  • Use simply python script attached ("ProcessTimeScan.py") to process the output log, averaging over the 20 events and plotting the ADC counts for a particular timing offset.

Miscellaneous informations

Electronic description

Collect the different parameters which should be tunned in order to be able to synchronise the board completly (different phase and delay etc...).

TODO List

  • FE:
    • Test behaviour of the intergator at saturation (how much goes to the next BxID)
    • Test with Cosmic bench.
    • Define the tests to be done for commissioning once connected with TFC
    • PVSS for the CROC and FE
    • Include Herschel project in LHCb
  • Tell1:
    • Frimeware (should decide on a raw bank format)
    • PVSS for Tell1
    • Test with the optical connection to the CROC
  • Trigger:
    • PVSS for the TVB
    • Commissioning together with CROC and FE
    • Commissioning with selection board

-- VictorCoco - 03 Apr 2014

Topic attachments
I Attachment History Action Size Date Who Comment
PNGpng CATAppli.png r1 manage 40.7 K 2014-04-07 - 17:10 VictorCoco  
PNGpng CATConfigFE.png r1 manage 24.7 K 2014-04-03 - 13:02 VictorCoco  
PNGpng CATTree.png r1 manage 23.3 K 2014-04-07 - 17:31 VictorCoco  
PNGpng CROCConfig.png r1 manage 266.6 K 2014-04-07 - 16:53 VictorCoco  
PNGpng FECRATE.png r1 manage 540.2 K 2014-04-03 - 11:51 VictorCoco  
PNGpng FEPGARam.png r1 manage 9.8 K 2014-04-10 - 09:01 VictorCoco  
Texttxt ProcessTimeScan.py.txt r1 manage 2.3 K 2014-10-21 - 10:58 DanielJohnson Timing scan example code
PNGpng RACK.png r1 manage 191.7 K 2014-04-03 - 11:57 VictorCoco  
PNGpng SpyEditor.png r1 manage 6.9 K 2014-04-10 - 09:14 VictorCoco  
PNGpng SpyEditor1.png r1 manage 7.1 K 2014-05-20 - 14:21 VictorCoco  
PNGpng SpyHCAL.png r1 manage 27.0 K 2014-07-10 - 11:10 VictorCoco  
PNGpng SpyInputHCAL.PNG r1 manage 51.1 K 2014-07-10 - 11:10 VictorCoco  
PNGpng TVB.png r1 manage 42.9 K 2014-07-10 - 11:12 VictorCoco  
PNGpng TVBMask.png r1 manage 4.9 K 2014-07-10 - 11:10 VictorCoco  
PNGpng WIENER.png r1 manage 214.9 K 2014-04-03 - 12:24 VictorCoco  
PNGpng resultNoise.png r1 manage 19.0 K 2014-05-20 - 14:26 VictorCoco  
PNGpng resultNoiseNosub.png r1 manage 19.0 K 2014-05-20 - 14:26 VictorCoco  
PNGpng resultRAMSimple.png r1 manage 49.3 K 2014-05-20 - 15:07 VictorCoco  
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Topic revision: r15 - 2014-10-21 - DanielJohnson
 
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