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Commissionning of the Herschel FE Crate

Timing scan

Dan please document

ADC conversion factor measurement

To redo

Reading RAM using external trigger.

In this test, RAMs are loaded in the FePGA and the CROC recieve an external trigger sequence. We then spy the RAM relased on the L0 arrival. That's the minimal setup to the next test.

Setup description

The external trigger is generated from a waveform generator. The waveform generator recieve a 20MHz clock from the CROC through the "clock div" output of the CROC front plane. By default the divided clock has a 1Hz frequency. This can be set to 20MHz in the CROC CAT panel by setting Clock-->Div to 2 instead of 40000000 and pressing Apply.

The generator provide a signal to where 25 ns at 0mV correspond to no trigger and 25ns at -800mV correspond to a trigger (???to check if this happens on rising edge or falling edge... expect a 1clk delay ion the wrong config). This output is directed to "Trig L0 Seq" input of the CROC front plane.


Setup the CROC (clock origin and RAM spying configuration), and fill the FE RAM (for detailled procedure, see "Hands-on CAT and the boards").

Prepare the generator so that a sequence is available when needed.

On the FE panel:

  • Press the ChannelB-->Calibration button (this tells the FE to be ready to send the RAM?)
On the CROC panel:
  • Press the General Control--> Enable Seq button. This tells the spyRAM to get ready to receive a L0 sequence. (validL0seq function of croc spyPGA)
  • Launch the trigger from the generator.
  • Press the Spy-->Transfer-->Start and then Spy-->Transfer-->View

-- VictorCoco - 03 Oct 2014

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Topic revision: r1 - 2014-10-03 - VictorCoco
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