This hardware is a variant of RichChimaera2. It combines RichChimaera2 and Tengja in a single PCB and uses the XC6SLX75T Spartan6 FPGA.

Software Installation

The trigger GUI, JRichTBTrigger2, is part of the RICHECKIT package. Check the RichEcKit topic for installation details.

When the GUI is started you will be prompted for the device to connect to. GUI interactions are almost identical to the Chimaera2+Tengja combination. Configuration is by XML files.


S675T trigger controller firmware

The latest firmware can be downloaded here.


This connector is used for the scintillator adapter board plug-in when the board is used as a trigger controller.


Pin Signal Mode Typical usage
Y5/AB5 TRGOUT(0)+/- LVDS toggle out Trigger
AA4/AB4 TRGOUT(1)+/- LVDS toggle out Trigger
K2/K1 GATEIN(0)+/- LVDS level in Gate
L3/L1 GATEIN(1)+/- LVDS level in Gate


Note that this connector usage has been modified for clock connections.

Pin Signal Mode Typical usage
AA18/AB18 TRGOUT(2)+/- LVDS toggle out Trigger
Y17/AB17 INTCLK+/- LVDS clock out Internal clock
L20/L22 EXTCLK+/- LVDS clock in External clock
K21/K22 GATEIN(3)+/- LVDS level in Gate


Pin Signal Mode Typical usage
AA16/AB16 TRGOUT(4)+/- LVDS toggle out Trigger
Y15/AB15 TRGOUT(5)+/- LVDS toggle out Trigger
J20/J22 GATEIN(4)+/- LVDS level in Gate
H21/H22 GATEIN(5)+/- LVDS level in Gate


Pin Signal Mode Typical usage
Y7/AB7 TRGOUT(6)+/- LVDS toggle out Trigger
AA6/AB6 TRGOUT(7)+/- LVDS toggle out Trigger
H2/H1 GATEIN(6)+/- LVDS level in Gate
J3/J1 GATEIN(7)+/- LVDS level in Gate


The firmware implements a number of counters:

Index Counter name Description
0 External Tclk Number of rising edges on external clock input
1 Gated trigger Number of triggers for currently selected gated trigger

The counters are automatically reset when the Start button is pressed. Additional radio buttons are provided to reset the counters. The values of the counters are stored in the elog for each recorded run.

Trigger source selection

Radio buttons allow to select between trigger sources. The sources include an internal pulser and the scintillator coincidences. The labels are defined in XML.

Index Source
0 None
1 Pulser
2 None
3 None
4 Coincidence 0
5 Coincidence 1
6 Coincidence 2
7 Coincidence 3

Gate input selection

The connected readout boards return a gate signal which are combined in the logic to inhibit triggers if any of the readout boards is not ready. Active gate sources should be enabled with the radio buttons provided. The labels of these buttons are defined in XML.

Variable pulser frequency

The Pulse delay textfield can be used to vary the frequency of the pulser. The allowed range is from 10 to 65535. For normal operation the pulser should be set to the order of 100kHz, corresponding to setting 100. At higher frequency (lower delay), the ethernet switch discards packets and the online data processing may experience difficulties keeping up. The delay is set in steps of 100ns in the current version of the firmware.

Deadtime control

For reliable triggering it is essential to set a minimum trigger deadtime to veto triggers until the hardware is ready to respond to the next. This is especially important when several parts of the system are running synchronously (e.g. tracker, RICH and beam scintillators). For example, with the RICH upgrade readout in TAE mode sending 23 time slots, the deadtime can be used to enforce a minimum spacing between triggers of 23 times 25ns (575ns). The deadtime setting in the trigger board is an integer with each step being 100ns so in this case, a setting of at least 6 (i.e. 600ns) should be used, more to be safer. The allowed range is 1-511. The deadtime can also be used to limit the rate to reduce packet loss in the network switch.


The CbS675t register map can be viewed here.
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Topic revision: r19 - 2020-02-28 - StephenWotton
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