Hands-on CAT and the boards

An easy one to start: Recording noise in the CROC

  • Open CAT and the appropriate config file (see previously). Open the configuration for the CROC and FE.
  • In the FE panel, under Front-End-->Subtraction, make sure one of the two subtraction scheme is selected (otherwise we collect the pedestal linked to the crate). To validate the changes press Apply.
  • In the CROC panel L0/ChannelB-->L0, configure the L0 sequence, for example:
    • L0 Number : how many L0 to produce, let's put 15
    • L0 Delay: delay between the signal triggering the L0 and the first L0 (relevant for L0 from the front face), let's keep it to 11.
    • L0 Frequency: how often a L0 is sent, let's put it to 1 ( ie one clock without between 2 L0).
  • Tell the CROC spy RAM what we want to spy. In to the CROC panel:
    • In specify the number of L0 to spy in Spy-->L0 (15 this time), press Apply
    • Select the Front end to be spied (FEB slot 6 for FEB 4 and FEB slot 14 for FEB 11)
    • Go to CROC config, in L0/ChannelB-->Spy-->Spy Table click on Edit.
    • This panel allow to choose which channel to spy and which L0.
    • For now we will spy first channel in each oif the 15 L0 recieved: Click on 00, it will select all the triggers correspoinding to the channel 00. Then click Select to validate it and Header and CtrlWd so that we also see the header and control words. Press OK.
    • In L0/ChannelB-->Spy-->Spy Table click the Config button to apply the previous step.

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  • Now we can start the sequence which requires to launch a L0 signal and read the CROC RAM. This is done all in one by pressing Aquisition button in L0/ChannelB-->Spy-->Transfert.
  • A panel pops up containing the word we asked to be spied:
    • Looking at the count of the BcID, we can notice: * That the BcID counts every 2 value. That's because there is a L0 only every 2 clock counts (L0 Frequency at 1). Important to check to see if the sequence is the expected one. * That for the channel 0 the data word is at 256 (...) and the trigger one at 0 (...)

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  • If we repeat without the subtraction:

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Load RAM and read them in CROC spy

Note on the RAM: In the CROC spy RAM, the channel 00, 08, 16, 24, correspond to the channel 0,1,2,3 of the FE!

  • Open CAT and the appropriate config file (see previously). Open the configuration for the CROC and FE.
  • Set the clock to be generated by the CROC. In the CROC panel-->L0/ChannelB pannel-->Input, select CROC and then apply (Buttons of L0 and Channel B should become green)
  • Configure the FEPGA:
    • Make sure Front-End-->Subtraction is on "No subtraction" (otherwise it mess up the RAM), Front-End-->TestMode-->Selection is on Physics Mode. To validate any changes press Apply.
    • Make sure Front-End-->RAM Advance is on "Clock". To validate any changes press Apply.
    • In order to be able to see something, we will put the "Enable Loop" so that the RAM is sent over and over after it is started by receiving the ChannelB calibration word. BUT this should be done after the RAM are loaded (otherwise they get written in random places...).
  • Load the RAM in the FEPGAs. Go to the FE panel:
    • Make sure "Enable Loop" is disabled. If it is clicked, unclick it and press "Apply".
    • In Front-End-->Channel Settings, press "Toggle ADC" (the FPGA will send a RAM when receiving a calibration word, instead of treating the ADC output) and "Apply".
    • In Front-End-->ADC Pattern, press the Browse button to select a RAM file. For this test we start with FEPattern_1.ram
    • Load will load the file in the software, Send All will send it to all the FE (Send plus a FEPGA will send it to a single FEPGA )
    • Read and the View, allow to inspect the RAM (View only allow to inspect the RAM which have been loaded but Read first read it from the RAM so one is sure of what is in the RAM).
    • In this RAM, channels are all empty except every 8 clock, where the channels are equal to 0xFFF. The first word start at the 5th clock count.
    • Now reactivate the loop by ticking the "Enable Loop" option and pressing "Apply"

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  • In the CROC panel L0/ChannelB-->L0, configure the L0 sequence. We take the same config as previous test, but with L0Frequency of 0 (ie a L0 at every clock count), press "Apply Settings"
  • Tell the CROC spy RAM what we want to spy. Go to the CROC panel:
    • Select the Front end to be spied (FEB slot 6 for FEB 4 and FEB slot 14 for FEB 11)
    • Go to CROC config, in L0/ChannelB-->Spy-->Spy Table click on Edit.
    • Here we will spy the same Channel 0 of Feb 4, for all 15 L0 we create, as in previous test.
    • In L0/ChannelB-->Spy-->Spy Table click the Config button to apply the previous step.
    • This panel allow to choose which channel to spy and which L0.
  • Send a ChannelB calibration word to the FE to say the FE to start sending the RAM.
  • Now we can start the sequence which requires to launch a L0 signal and read the CROC RAM. This is done all in one by pressing Aquisition button in L0/ChannelB-->Spy-->Transfert.

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Spying RAM from the TVB

The TVB contains two types of RAM. Input RAM which can be used to test the logic with definite signals and output RAM which allow to check the response of the TVB to FE signals or to input RAMs. Here is explained the procedure to read the output of the TVB for given input RAM in the FE:
  • Open CAT and load a configuration file with the TVB (CATLAL/HerschelDevTVB.cdf in our case)
  • Open the configuration for the CROC and FE.
  • Set the clock to be generated by the CROC. In the CROC panel-->L0/ChannelB pannel-->Input, select CROC and then apply (Buttons of L0 and Channel B should become green)
  • Load RAM to the FE (see previously)
  • Open the CAT TVB panel (from the tree viewer, open the master, select Validation, and click "Edit Element").
  • We use the HCAL logic, in the "Delay Fifo HCAL" mask all channels which are unused (in this config only ECAL4 is unmasked)
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  • Then press "Apply Register" to write the fifo register in the board, and "Get Register" to check they have been written.
  • In "HCAL Ram" tab, press "Output Data". It opens the panel to control the output RAM
  • By pressing "Spy", the CROC sends the L0 sequence so that the FE RAM are released and pass throught the TrigPGA of the FE which send the max and sumET to the TVB. The TVB treat it and the result is stored in the Output RAM
  • By pressing "Read" the content of the RAM is displayed.
  • Note that "Spy" will also store the inputRAM, which can be displayed by pressing "Input RAM -> Read"

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-- VictorCoco - 03 Oct 2014

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