This program is used to set up the DAQ trigger sources. It can be run standalone but it should normally be started from JRichEcControl.

Software Installation

The trigger GUI is part of the RICHECKIT package. Check the RichEcKit topic for installation details.

Using the Main->Devices... menu, select the ID of the connected trigger device (it is usually on a label on the underside of the board). Restart the GUI.


The hardware consists of a Chimaera2 FPGA board, Tengja breakout/adapter board and scintillator plug-in. The photograph shows the boards assembled in the 2017 beam test configuration which exposes the Tengja J6 connector.

The trigger board functions also as a 4-channel coincidence unit when coupled with the Tengja board and scintillator plugin module as shown. See the JCosmixerDepp topic for details. Any of the six programmable coincidences may be selected as the DAQ trigger source in the JRichTBTrigger main panel.


The latest firmware can be downloaded here.

Chimaera2 PL1 2x5 pin header

For 2017 beam tests the pin functions are assigned as follows:

Pin Signal Mode Typical usage
AA8/AB8 TRGOUT+/- LVDS toggle out Tracker A/B
Y9/AB9 TRGOUT+/- LVDS toggle out Tracker A/B
AA10/AB10 TRGOUT+/- LVDS pulse out Telescope or miniDAQ
W12/Y12 TRGIN+/- LVDS In External trigger source (called LVDS on GUI)

For 2018 beam tests the pin functions are assigned as follows (miniDAQ synchronous trigger):

Pin Signal Mode Typical usage
AA8/AB8 TRGOUT+/- LVDS pulse out (delayed) Telescope or miniDAQ
Y9/AB9 TRGOUT+/- LVDS pulse out (prompt,synchronous to W12/Y12) MiniDAQ trigger
AA10/AB10 TRGOUT+/- LVDS pulse out (delayed) Telescope or miniDAQ
W12/Y12 ExtClk+/- LVDS In External global clock input

LEMO connectors

Pin Function Mode

LEMOTOP may be used as an LVTTL pulse to trigger an LED or LASER pulser. It is driven synchronously to the trigger outputs but can be independently enabled or disabled from the panel.


For the 2017 beam test configuration, the PDMDB master link I2C can be driven from the Tengja J6 connector as follows:

Pin Signal Mode Typical usage
70 SDA0 I2C InOut PDMDB0 master link configuration
69 SCL0 I2C Out PDMDB0 master link configuration
76 SDA1 I2C InOut PDMDB1 master link configuration
75 SCL1 I2C Out PDMDB1 master link configuration


The trigger GUI displays a number of counters:

Counter name Description
External Tclk Number of rising edges on external clock input
Gated trigger Number of triggers for currently selected gated trigger
Ungated beam Number of ungated beam triggers after input conditioning
Gated beam Number of gated triggers after input conditioning
Telescope Number of trigger pulses to telescope
Gated pulser Number of gated pulser triggers

The counters are automatically reset when the Start button is pressed. Additional radio buttons are provided to reset the counters. The values of the counters are stored in the elog for each recorded run.

Trigger and DB selection

Radio buttons allow to select between three trigger sources (Pulser, Beam or FEB) or None. The connected DBs should be ticked in the GUI.

DB TB name Tengja trigger Tengja gate
0 JT-AB J5(3,4) J5(7,8)
1 JT-CD J5(5,6) J5(9,10)
2 ST-AB J2(3,4) J2(7,8)
3 ST-CD J2(5,6) J2(9,10)
4 SB-CD J3(3,4) J3(7,8)
5 SB-AB J3(5,6) J3(9,10)
6 JB-CD J4(3,4) J4(7,8)
7 JB-AB J4(5,6) J4(9,10)
8 Tracker-A J6(89,90)
9 Tracker-B J6(83,84)

Variable pulser frequency

The Pulse delay textfield can be used to vary the frequency of the pulser. The allowed range is from 10 to 65535. For normal operation the pulser should be set to the order of 100kHz, corresponding to setting 100. At higher frequency (lower delay), the ethernet switch discards packets and the online data processing may experience difficulties keeping up. The delay is set in steps of 100ns in the current version of the firmware.

Deadtime control

For reliable triggering it is essential to set a minimum trigger deadtime to veto triggers until the hardware is ready to respond to the next. This is especially important when several parts of the system are running synchronously (e.g. tracker, RICH and beam scintillators). For example, with the RICH upgrade readout in TAE mode sending 23 time slots, the deadtime can be used to enforce a minimum spacing between triggers of 23 times 25ns (575ns). The deadtime setting in the trigger board is an integer with each step being 100ns so in this case, a setting of at least 6 (i.e. 600ns) should be used, more to be safer. The allowed range is 1-511. The deadtime can also be used to limit the rate to reduce packet loss in the network switch.


The JRichTBTrigger register map can be viewed here.

New timing trigger TB2018

GUI installed in richtbuser account on lbrichtb.

Run it with

cd ~richtbuser/Public/Java/Trigger2Kit
java -Djava.library.path=. -jar JRichTBTrigger.jar

Requires external clock (from miniDAQ/muDAQ) connected to Y12/W12.

Set pulse widths to 10 (100ns). Set deadtime to 5 (500ns) or greater.

Firmware is not loaded permanently into flash. On power cycle, reload the firmware as follows (stop the trigger GUI first):

cd ~richtbuser/Public/Java/JAVAKIT
java -Djava.library.path=. -jar XilinxDjtg.jar

  • Click OK to connect to the trigger board.
  • Click Choose file to select the firmware.
  • Click Load FPGA to program the FPGA.
  • Exit program when done.

Use firmware richtbtrigger-x4-v3.bin.

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Topic revision: r16 - 2020-01-03 - StephenWotton
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