Documentation for L0 Calorimeter hardware

Cavern

Ethernet Cables

These cables are used to exchange trigger information between boards located on the calorimeter platform. The list of all cables is here: TriggerLabels.xls.

Test of cables:

From To Tested Comments
HCAL22 HCAL22 DONE 3 Sep 2007 OK
HCAL23 HCAL23 DONE 4 Sep 2007 OK
ECAL12 ECAL12 DONE 25 Sep 2007 OK
ECAL14 ECAL14 DONE 24 Oct 2007 OK
ECAL13 ECAL14 DONE24 Oct 2007 OK
ECAL14 ECAL13 DONE 24 Oct 2007 OK
ECAL9 ECAL8 DONE 25 Oct 2007 OK
ECAL10 ECAL9 DONE 31 Oct 2007 Cable 4CCLALTS100001 was bad: OK after replugging
ECAL10 ECAL10 DONE 31 Oct 2007 Connector corresponding to cable 4CCLALTS100092 is bad: problem identified in FE Board, board now replaced: OK
ECAL11 ECAL11 DONE 25 Oct 2007 OK
ECAL11 ECAL12 DONE 25 Oct 2007 OK
ECAL12 ECAL11 DONE 31 Oct 2007 OK
HCAL22 ECAL8 DONE 24 Oct 2007 OK
HCAL22 ECAL9 DONE 24 Oct 2007 OK
HCAL22 ECAL10 DONE24 Oct 2007 OK
HCAL23 ECAL10 DONE 24 Oct 2007 OK
HCAL23 ECAL11 DONE 24 Oct 2007 OK
HCAL23 ECAL12 DONE 24 Oct 2007 OK
HCAL23 ECAL13 DONE 24 Oct 2007 OK
HCAL23 ECAL14 DONE 24 Oct 2007 OK
PRS3 ECAL14 DONE 19 Dec 2007 OK (4CCLALTS100301 replugged at the correct place)
PRS0 PRS0 DONE 29 Jan 2008 OK
PRS1 PRS1 30 Jan 2008 a backplane RJ45 connector is disabled (cable 4CCLALTS100326)
PRS2 PRS2 DONE 29 Jan 2008 OK
PRS3 PRS3 DONE 29 Jan 2008 OK
PRS1 PRS0 DONE 30 Jan 2008 OK (TTCrq clock issue fixed)
PRS2 ECAL11 DONE 31 Jan 2008 OK
PRS2 ECAL12 DONE 01 Feb 2008 OK
ECAL15 ECAL16 DONE 11 Feb 2008 OK
ECAL16 ECAL16 DONE 11 Feb 2008 OK
ECAL16 ECAL15 DONE 11 Feb 2008 OK
ECAL17 ECAL17 DONE 11 Feb 2008 OK
ECAL17 ECAL18 DONE 11 Feb 2008 OK
ECAL18 ECAL17 DONE 11 Feb 2008 OK
ECAL18 ECAL18 DONE 11 Feb 2008 OK
ECAL21 ECAL20 DONE 12 Feb 2008 OK
ECAL20 ECAL19 DONE 12 Feb 2008 OK (Cable 4CCLALTS100412 replaced by new cable)
ECAL19 ECAL19 DONE 12 Feb 2008 OK
HCAL24 HCAL24 DONE 21 Feb 2008 OK
HCAL25 HCAL25 DONE 21 Feb 2008 OK (4CCLALTS100751 replugged at the correct place)
PRS0 PRS0 DONE 21 Feb 2008 OK
PRS6 PRS6 DONE 21 Feb 2008 OK
PRS7 PRS6 DONE 21 Feb 2008 OK
PRS7 PRS7 DONE 21 Feb 2008 OK
PRS4 PRS4 DONE 22 Feb 2008 OK
PRS5 PRS5 DONE 22 Feb 2008 OK
ECAL19 PRS6 DONE 20 Feb 2008 faulty FEB 102 replaced by FEB 029, cable 4CCLALTS100571 to replace
PRS6 ECAL19 DONE 21 Feb 2008 OK
PRS7 ECAL20 DONE 21 Feb 2008 OK
PRS7 ECAL21 DONE 21 Feb 2008 OK
PRS0 ECAL8 DONE 21 Feb 2008 OK
PRS0 ECAL9 DONE 21 Feb 2008 OK
ECAL20 PRS7 DONE 21 Feb 2008 OK
ECAL21 PRS7 DONE 21 Feb 2008 OK
ECAL8 PRS0 DONE 21 Feb 2008 OK
ECAL9 PRS0 DONE 21 Feb 2008 OK
ECAL10 PRS1 DONE 22 Feb 2008 OK
PRS1 ECAL10 DONE 22 Feb 2008 OK
PRS4 ECAL15 DONE 22 Feb 2008 OK
PRS4 ECAL16 DONE 22 Feb 2008 OK
PRS5 ECAL17 DONE 22 Feb 2008 OK
PRS5 ECAL18 DONE 22 Feb 2008 OK
ECAL11 PRS2 DONE 23 Feb 2008 OK
ECAL12 PRS2 DONE 23 Feb 2008 OK
ECAL14 PRS3 DONE 24 Feb 2008 OK
ECAL15 PRS4 DONE 24 Feb 2008 OK
ECAL16 PRS4 DONE 24 Feb 2008 OK
ECAL17 PRS5 DONE 25 Feb 2008 OK (4CCLALTS100580 & 4CCLALTS100581 replugged at the correct place)
ECAL18 PRS5 DONE 25 Feb 2008 OK
ECAL13 PRS3 DONE 28 Feb 2008 OK
PRS3 ECAL13 DONE 28 Feb 2008 OK

Optical Cables

Test of cables:

Electron Selection Board

Link From Connectivity BER 0dB BER 9dB Comments
1 ECAL8.0 DONE 15 Dec 2007      
2 ECAL9.0 DONE 15 Dec 2007      
3 ECAL13.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
4 ECAL14.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
5 ECAL13.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
6 ECAL14.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
7 ECAL8.1 DONE 15 Dec 2007      
8 ECAL9.1 DONE 15 Dec 2007      
9 ECAL11.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
10 ECAL12.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
11 ECAL11.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
12 ECAL12.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
13 ECAL20.0        
14 ECAL21.0        
15 ECAL15.0        
16 ECAL16.0        
17 ECAL15.1        
18 ECAL16.1        
19 ECAL20.1        
20 ECAL21.1        
21 ECAL17.1        
22 ECAL18.1        
23 ECAL17.0        
24 ECAL18.0        
25 ECAL10.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
26 ECAL10.1 DONE 15 Dec 2007      
27 ECAL19.0        
28 ECAL19.1        

Photon Selection Board

Link From Connectivity BER 0dB BER 9dB Comments
1 ECAL8.0 DONE 15 Dec 2007      
2 ECAL9.0 DONE 15 Dec 2007      
3 ECAL13.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
4 ECAL14.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
5 ECAL13.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
6 ECAL14.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
7 ECAL8.1 DONE 15 Dec 2007      
8 ECAL9.1 DONE 15 Dec 2007      
9 ECAL11.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
10 ECAL12.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
11 ECAL11.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
12 ECAL12.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
13 ECAL20.0        
14 ECAL21.0        
15 ECAL15.0        
16 ECAL16.0        
17 ECAL15.1        
18 ECAL16.1        
19 ECAL20.1        
20 ECAL21.1        
21 ECAL17.1        
22 ECAL18.1        
23 ECAL17.0        
24 ECAL18.0        
25 ECAL10.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
26 ECAL10.1 DONE 15 Dec 2007      
27 ECAL19.0        
28 ECAL19.1        

Local pi0 Selection Board

Link From Connectivity BER 0dB BER 9dB Comments
1 ECAL8.0 DONE 15 Dec 2007      
2 ECAL9.0 DONE 15 Dec 2007      
3 ECAL13.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
4 ECAL14.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
5 ECAL13.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
6 ECAL14.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
7 ECAL8.1 DONE 15 Dec 2007      
8 ECAL9.1 DONE 15 Dec 2007      
9 ECAL11.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
10 ECAL12.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
11 ECAL11.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
12 ECAL12.1 DONE 15 Dec 2007   DONE 15 Dec 2007  
13 ECAL20.0        
14 ECAL21.0        
15 ECAL15.0        
16 ECAL16.0        
17 ECAL15.1        
18 ECAL16.1        
19 ECAL20.1        
20 ECAL21.1        
21 ECAL17.1        
22 ECAL18.1        
23 ECAL17.0        
24 ECAL18.0        
25 ECAL10.0 DONE 15 Dec 2007   DONE 15 Dec 2007  
26 ECAL10.1 DONE 15 Dec 2007      
27 ECAL19.0        
28 ECAL19.1        

Global pi0 Selection Board

Link From Connectivity BER 0dB BER 9dB Comments
1 ECAL8.0        
2 ECAL9.0        
3 ECAL13.0        
4 ECAL14.0        
5 ECAL13.1        
6 ECAL14.1        
7 ECAL8.1        
8 ECAL9.1        
9 ECAL11.0        
10 ECAL12.0        
11 ECAL11.1        
12 ECAL12.1        
13 ECAL20.0        
14 ECAL21.0        
15 ECAL15.0        
16 ECAL16.0        
17 ECAL15.1        
18 ECAL16.1        
19 ECAL20.1        
20 ECAL21.1        
21 ECAL17.1        
22 ECAL18.1        
23 ECAL17.0        
24 ECAL18.0        
25 ECAL10.0        
26 ECAL10.1        
27 ECAL19.0        
28 ECAL19.1        

From To Tested Comments
ECAL C-side TCASBHMA 1->12 DONE 15 Dec 2007 OK BER, redo input 2 (ECAL13)

HCAL Front-End Board

List of boards with old trigger FPGA version:

Crate Slot (trigger slot from 0 to 15)
HCAL22 3
HCAL22 4
HCAL22 5
HCAL22 7
HCAL22 8
HCAL22 9
HCAL22 10
HCAL22 12
HCAL23 1
HCAL23 7
HCAL23 12
HCAL24 1
HCAL24 14

PS/SPD Front-End Board

Trigger Cables test :


  • PS/SPD TOP neighbours input : the allowed phase ranges, for both C-side and A-side, can be found here: cabling_PS2PS.xls.
  • ECAL address inputs : the allowed phase ranges, for both C-side and A-side, can be found here: cabling_ECAL2PS.xls.
  • PS/SPD - TVB link : the phase ranges allowed for inputs of the TVB can be found in TVB section.

Crate synchronisation :


CROC boards allow to align in time the clocks (and the calibration signals) of the different crates by two options : "fine delay" option (phase shift from 0 to 23,9ns) and "coarse delay" (latency from 0 to 16 clock cycles). For each CROC board, "Fine delay" option has been set for synchronising clocks (channel A) and synchronising L0 trigger signals (channel B). No difference in clock cycles has been observed.

Crate "Fine delay" value Comment
PRS7 value = 30 the reference
PRS6 value = 35  
PRS5 value = 20  
PRS4 value = 30  
PRS0 value = 30 CROC "ClkFeb" output is disabled. So "ClkDiv" output has been used.
PRS1 value = ? all CROC outputs are disabled
PRS2 value = 55  
PRS3 value = 45  

Internal Time alignment of the Trigger path:


Crate Board FEPGA PIPELINE - PS SPD LOLAT TRIGPGA PS/SPD TALAT TRIGPGA TOP TALAT TRIGPGA RIGHT TALAT
PRS2 ALL += 2 3 0 1
PRS3 ALL += 2 3 0 1
PRS4 ALL += 2 3 0 1
PRS5 ALL += 2 3 0 1
PRS6 FEB04 +=1 4 1 2
PRS6 FEB05 +=1 4 0 2
PRS6 FEB06 +=1 4 1 2
PRS6 FEB07 +=1 4 0 2
PRS6 FEB08 +=1 4 0 1
PRS6 FEB09 +=2 3 0 2
PRS6 FEB10 +=1 4 0 1
PRS6 FEB11 +=2 3 0 0
PRS7 FEB01 +=1 4 1 2
PRS7 FEB02 +=1 4 0 2
PRS7 FEB03 +=1 4 0 2
PRS7 FEB04 +=1 4 0 2
PRS7 FEB05 +=1 4 0 2
PRS7 FEB06 +=1 4 0 2
PRS7 FEB07 +=1 4 0 0
PRS7 FEB08 +=1 4 0 1
PRS7 FEB09 +=2 3 0 1
PRS7 FEB10 +=2 3 0 0
PRS7 FEB11 +=3 2 0 1
PRS7 FEB12 +=2 3 0 1
PRS7 FEB13 +=2 3 0 1
PRS7 FEB14 +=2 3 0 0

Remaining : PRS0 & PRS1

Time alignment of the Trigger path {PRS/SPD - ECAL} :


Work in progress ...

Validation Board

Validation board installed on cryo side
Crate TVB number Tested
8 0 DONE27 Oct 2007
  1 DONE27 Oct 2007
9 2 DONE27 Oct 2007
  3 DONE27 Oct 2007
10 4 DONE27 Oct 2007
  5 DONE27 Oct 2007
11 6 DONE27 Oct 2007
  7 DONE27 Oct 2007
12 8 DONE27 Oct 2007
  9 DONE27 Oct 2007
13 10 DONE27 Oct 2007
  11 DONE27 Oct 2007
14 12 DONE27 Oct 2007
  13 DONE27 Oct 2007

D2 Barrack

Control PC

D3 Barrack

All L0Calo hardware are in rack D3B01 (Selection Boards and patch panels) except the TELL1s which are in rack D3B02.

D3B01.jpg

Selection Boards

Things to fix in the firmware:

  • Send IDLEs to the L0DU when the local BCID >= N, where N is a 12 bit register accessible via ECS FIXED
  • Align input and result in the buffer sent to the TELL1
  • Remove "jitter" in L0Accept
  • Put the channel at 0 when it is masked

Settings for SB:

  • BCId Delay: Address=0xn103000, Value=0x00000030 (Delay in L0DU: 7)
  • Master Hadron: Address=0x6101000, Value=0x70000000, Address=0x6103000, Value=0x80000000
  • Slave1 Hadron: Address=0x6101000, Value=0x000C0000, Address=0x6103000, Value=0x00000000
  • IDLES for L0DU: Address = 0x6104000, Value=0x00DE9000 (==> 3 IDLES)
  • Type for TELL1: Address = 0x6108000, Value = 0x00000001
  • Latency: Address = 0x6109000, Value=0x00000050

TELL1s

Optical Cables

These cables are used to connect the output of the optical patch panels in the D3B01 rack (that is to say the output of the Trigger Validation Boards and of the SPD Multiplicity Boards) to the input of the Selection Boards, and to connect the Selection Boards to the L0DU and the TELL1s. The list of optical cables and the map of connections in the patch panels are here: OpticalL0CaloCablesD3.xls.

Network Cables

-- PatrickRobbe - 30 Jul 2007

Topic attachments
I Attachment History Action Size Date Who Comment
JPEGjpg D3B01.jpg r4 r3 r2 r1 manage 70.6 K 2007-07-30 - 16:18 PatrickRobbe Picture of D3B01 rack
Microsoft Excel Spreadsheetxls OpticalTriggerL0CaloCables-Children.xls r1 manage 240.5 K 2007-07-30 - 15:40 PatrickRobbe List of L0Calo optical cables in the barrack and connections in the patch panel
Microsoft Excel Spreadsheetxls TriggerLabels.xls r1 manage 409.5 K 2007-07-30 - 15:34 PatrickRobbe List of ethernet L0Calo trigger cables
PDFpdf backplane6u_proto1.pdf r1 manage 3231.5 K 2009-02-04 - 15:16 PatrickRobbe  
Microsoft Excel Spreadsheetxls cabling_ECAL2PS.xls r2 r1 manage 70.0 K 2008-02-27 - 18:24 EricConte  
Microsoft Excel Spreadsheetxls cabling_PS2PS.xls r1 manage 44.5 K 2008-02-25 - 20:24 EricConte  
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Topic revision: r49 - 2009-02-04 - PatrickRobbe
 
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