The latest production level project in SSB2 is PVSS3.6, R2DAQL0 running on lbriwico01 under the lhcbrich account

L0 Board Instructions (02/05/07)

Starting the project

run s3.vbs (FSM) from the desktop

press enter

start PVSS project R2DAQL0

run "device editor and navigator panel" from the PVSS console

go to FSM tab

start/restart the FSM

left click then right click on R2DAQL0S1

go to "view"

double click on Column1

Go to the PVSS3.6 console, check that all PVSS00DIM managers are running.

The rest of this manual requires that the LV_Lo and LV_Hi are on, and that the LV regulators are powered up. See Antonis for the instructions.


In the new panel which pops up we can power on the regulators and configure the L0 boards, to do this.


Configuring L0 boards

Click on the lock icon in the panel named 'Column1 Top'. Click 'take'

Click on the Column1 state (currently should be NOT_READY) underneath 'System' in the panel which is named "R2DAQL0:R2DAQL0:manager1". Click 'configure'.

any errors can be recovered and then configuration tried again. Use 'recover' in preference to 'reset' if the power is on.

Once the boards move to "ready", they will take data.

To see the pint test pattern on all chips, click the pint test pattern button in the FSM panel fo rthe column S1. You will need to click 'GetPint Defaults' to activate this button.

To set Alice mode, click the relevant button. Again you will need to click 'GetPint Defaults' to activate this button.

To set a special test pattern of lines of pixels on each of the pixel chips, click the chips to activate on the RHS of the FSM panel and then "Set". Alternatively, just click test all to switch it on for all chips. The odin needs to be 'timed in' for this to work. The Odin settings are also on the twikki.

Switch OFF

No special configuration is needed before switching off.

Advanced Configuration

To access advanced confiuration for an L0 board, double click on the L0 board to configure in the FSM panel for Column 1. The relevant chips on the board can be configured by single clicking on the buttons associated to that chip in the new panel that pops up.

- HPDs

The most notable thing one might want to look at is the HPD test pattern, this can be set by clicking on the "HPD0" and "HPD1" buttons.

Click "Apply Test Mask" in the new panel. This puts a few lines of test pixels. note :The test pixels will only be seen in data if time alignment and/or odin is configued properly to see them.

It is also possible to manually mask and test individual pixels if this is useful. Click on the pixel to mask in the green representation of the pixel chip, left. The masking and testing is done alice pixel by alice pixel. Access the sub pixel to mask in the Sub Pixel menu, click the check box and then remember to click OK to apply the change. This button may be greyed out if the special test pattern is on.

The entire chip can be masked or tested by clicking the buttons bottom left. This button also may be greyed out if the special test pattern is on.

Thresholds can be changed by selecting the top left combi box and moving to the PRE_Vth selection. Write the new threshold value (integer setting) into the "Value (dec)" box. Click "Write". A higher threshold is gained by writing a lower PRE_VTH.


The pint config & reset registers can be set from here, as can the strobe and test pulse registers. Write "1" (or better, "385") into the config register to generate the pint test pattern.

The coarse timing of the test pulses can also be changed from here.


For test pulse runs, one might want to change the fine timing of the test pulse. Change Clock Des 2.

For fine timing with respect to the external light source (laser, cherenkov radiation particles) Change Clock Des 2 and TTCrx coarse delay.



Error recovery. (assumes basic knowledge of PVSS)

In the FSM, the boards may enter error state for several reasons.

Wrong recipe

If you are using a unique recipe, try configuring again with the run_mode =PHYSICS

External programs not running or hung

Procedure - check DNS server is running as a DOS window in te task bar.

Check RICHL0_Dim server is running as a DOS window in the task bar.

These can be started by running S3.vbs form the desk top

SPECS has hung

Close SPECS server and DIM server. Restart them by running s3.vbs from the desktop.

If this fails, close the DIM server but not the specs server. Power off the column, power on the column andt then run s3.vbs again. Reconfigure.

PVSS managers failed

The PVSS00Dim manager may not be running,

Open a PVSS console, look near the bottom of the list of managers for the manager PVSS00DIM with the parameters

-dim_dp_config RICHL0 -dim_dns_node <DIMDNSNODE> -num 9.

In the ssb2 the DIMDNSNODE is lbriwico01

Check these parameters and start the manager.


Time out

If the error is none of the above, it might be a time out error. Try configuring only 1 board at a time.

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Topic revision: r3 - 2007-10-29 - StephenWotton
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