Wiki page for the SPECS

To Do List

• Put documentation in EDMS

Current problems under investigation

• Mezzanine:
  • When reading in DMA mode, if one asks for more than 64 bytes, the mezzanine is blocked (sends back continuous data)
  • When reading in JTAG mode, fixed patterns (0011 0011 0011 0011 0011) are inserted at random positions.

• Master:
  • Master is unstable in PCI slot 6.
  • Slot number reported by the software is not the physical location on the PC.
  • Enable write bit does not report the correct Emitter FIFO size.
  • PCI Specs frames should be revisited.

• Glue:

Problems fixed

• Mezzanine:
  • 21 Sep 2005: DCU usage. The specs_clock_out line is cut and not used anymore for the DCU. The DCU uses a new dedicated line coming from a free pin. The external reference resistor is changed to 120 kOhms. A new firmware is needed (date 2209.).

• Glue:
  • 22 Sep 2005: In I2C write, the glue sends an answer back. FIXED This was an incompatibility between different component libraries.
  • 04 Oct 2005: Long I2c frames do not work. FIXED in firmware 041005.

Development firmware files for the Master

date	files	Change log
22/09/2005	pof/sof	Correct DMA reading
21/10/2005	pof	Version for multi master test

Development firmware files for the Slave

date	files	Change log
22/09/2005	pof/sof	To be used with modified mez. for DCU
29/09/2005	pof/sof	Firmware with date 0609, correct chaining in principle

Development firmware files for the Glue

date	files	Change log
22/09/2005	txt	Correct I2C write problem
03/10/2005	txt	Version used to study long I2C frames
04/10/2005	stp	Version to use long I2C frames

Private documentation

Position of oscillo points

For Master #1, top line :

• hole # 3 from right : enable read
• hole # 4 from right : enable write

bottom line :

• hole # 2 from right : ready

SPECS Frames

Firmware programming with PCI

The Specs master firmware can be programmed using the PCI. The PLX9030 builds JTAG frames and send it to the Specs Master FPGA through GPIO.

To do this:

• The firmware is written in .jam format
• The JAM Player of Altera is used (it can be downloaded from the Altera web site together with the source files.)
• One needs to modify the JAM Player to use the GPIO pins of the PLX9030 to make the JTAG signals instead of the Altera Programmer:

JAMPORT.H: changer dans ce fichier pour construire un executable Linux. Par defaut sans rien changer, on produit un executable WINDOWS.

Le programme principal est dans JAMEXEC.C: Pour executer le programme, il faut taper:

jam.exe -aCONFIGURE -p<port> [Nom du fichier .jam]

Pour le Specs, il faut remplacer -p par le numero du slot a programmer.

Les modif sont a faire dans JAMSTUB.C:

La fonction qui fait le travail est jam_jtag_io.

Il faut la remplacer par une fonction comme ceci (voir fichier readme.txt de la distribution):

int jam_jtag_io(int tms, int tdi, int read_tdo)
{
   int data = 0;
   int tdo = 0;

   if (!jtag_hardware_initialized)
   {
      initialize_jtag_hardware();
      jtag_hardware_initialized = TRUE;
   }
   data = ((tdi ? 0x40 : 0) | (tms ? 0x02 : 0));
   write_byteblaster(0, data);

   if (read_tdo)
   {
      tdo = (read_byteblaster(1) & 0x80) ? 0 : 1;
   }
   write_byteblaster(0, data | 0x01);
   write_byteblaster(0, data);
   return (tdo);
}

Elle appelle en premier la fonction initialize_jtag_hardware() : c'est ici qu'il faut ouvrir le Specs et recuperer un HANDLE sur la carte Specs qui permettra de faire des acces sur cette carte par la suite.

Ensuite:

1. il faut positioner un meme temps:

• TDI a 0, si la variable tdi est 0, et TDI a 1 si tdi est different de 0
• TMS a 0, si la variable tms est 0, et TMS a 1 si tms est different de 0
• TCK a 0

1. il faut lire le TDO et mettre le resultat dans la variable tdo: 0 ou 1.

1. il faut positioner en meme temps:

• TDI a 0, si la variable tdi est 0, et TDI a 1 si tdi est different de 0
• TMS a 0, si la variable tms est 0, et TMS a 1 si tms est different de 0
• TCK a 1

1. il faut positioner en meme temps:

• TDI a 0, si la variable tdi est 0, et TDI a 1 si tdi est different de 0
• TMS a 0, si la variable tms est 0, et TMS a 1 si tms est different de 0
• TCK a 0

La correspondance GPIO -> JTAG est:

GPIO	JTAG
0	TDI
1	TDO
3	TCK
4	TMS
8	activation

Logbook

-- PatrickRobbe - 21 Sep 2005

Install new Specs master in PC-LHCB5 (add WinCvs, CMT, SpecsLib and SpecsUser in directory C:\Specs). Master #15 does not work (it seems we cannot access Plx9030 memory correctly) so we use master #6. Master is programmed with firmware with date 08092005. A command window (Command Specs) link is created on the desktop of the eleclhcb user.

We try with old glue on FeBoard #3. 50 % of the transactions contain errors (reading register #3).

---

-- PatrickRobbe - 22 Sep 2005

Modify mezzanines #114, #107 and #102 for DCU reparation and program with firmware 2209. It consists in cutting specs_out_clock line going to DCU and using a free output pin to connect to DCU input clock pin the Specs clock. The reference resistor has also been changed to 120 kOhms resistance.

Test mezzanines #114, #107 and #102 for DCU modifications. DCU is at address 0. Channel 0 is set on Croquette to value 1.7 V, and channel 1 to 0.75 V. The values read are correct (but it is preferable to use Low Input Range to have better converted values). DCU have to be calibrated.

Mezzanine	Mean of 1000 acq in LIR	Sigma	Deviation maxi
107 (ch 0: 1.750 V)	3759.23	0.45	1.78
107 (ch 1: 0.756 V)	1607.16	0.38	1.16
114 (ch 0: 1.750 V)	3751.99	0.34	3.01
114 (ch 1: 0.756 V)	1608.10	0.34	1.11
102 (ch 0: 1.750 V)	3732.72	0.47	1.25
102 (ch 1: 0.756 V)	1595.42	0.50	1.40

For this test, we use the program testDCU.

Test of Specs chaining with the repaired mezzanines #114. Access new Fe Board Glue (address 14) via the mezzanine #114. Test random read/write on Glue register #3 with test program. We obtain 0 error on 1000000 events.

Mezzanines #107 and #102 do not have R51 resistances to work in chaining. Mezzanine #114 has still R51 resistance to work as master.

Mezzanines #107 and #102 are tested as slaves with automatic commutation and in master mode also and they work correctly in all modes.

Send mezzanines repaired for DCU to (with firmware 2209):

• Tom, #114
• Anatoly, #102
• Daniel, #107

Add to CVS of SpecsUser modifications to use the correct conversion constants for the DCU acquisition. However it is probably better to calibrate each DCU and do the conversion on its own.

---

With the APA Glue on the new FE Board: reading/writing of parallel registers work correctly. I2C does not. The problem we observe is that the GLUE emits data even in the case of a write I2C access. This is fixed by Daniel with the last version of GLUE firmware. Everything is OK now.

---

-- PatrickRobbe - 27 Sep 2005

Install CAT on pc-lhcb5 with the latest version of SpecsLib / SpecsUser v6r0-v3r3 from http://lhcb.lal.in2p3.fr/Specs/WindowsFiles/DistribWindows-v6r0-v3r3.zip. This is to use the new master with the new FE card.

---

-- PatrickRobbe - 29 Sep 2005

Study the problem of the enable write. We observe that the size of the Emitter FIFO in the Specs seems to be limited to 0xFD instead of 0xFF: that is why the 2 last 32 bit words we send to the SPECS are lost. Solution : modify the SpecsLib library to take into account that the maximum size of the emitter RAM is 0xFD.

Study the long I2C frames. It does not work in write with more than 2 frames. We use a new Glue progam (the old one was https://twiki.cern.ch/twiki/pub/LHCb/LHCbSpecs/Glue_050905.txt) to redirect the SCL of the Fe PGA #0 to a probe of the FE BOARD.

We use a new FE BOARD and program the Mezzanine with firmware 0609, and glue with firmware []. Problem : when we chain 1 short I2C frame and then 1 long I2C frame. We use firmware of Glue 0310.

---

-- PatrickRobbe - 03 Oct 2005

Study long I2C frames with the Glue. We observe that Glue is sensitive to clock constraints. Long frames are working if we chain 1 long + 1 short. With 2 long + 1 short in writing, it does not because SCL is not maintained low between the last 2 frames.

---

-- PatrickRobbe - 04 Oct 2005

Long I2C frames work now with the glue, with firmware 041005. We use the testRAM.cpp test program to test it. We write 90 random bytes to the Sequencer Spy RAM (NTA of the RAM is address 0x52, subaddress 0x4. Address of the RAM is 0x52, subaddress 0x5, the output select for the sequencer is 13). During the night we launch a test with 10000 * 90 random bytes write + 10000 * 90 read read with one single long I2C frame each.

There was a bug in the specs_i2c_read and specs_i2c_read_sub functions when used with long frames. The bug is fixed in CVS today and a new release is available on the Specs web page.

---

-- PatrickRobbe - 13 Oct 2005

Use Croquette (powered by 3.3 V) to measure I2C clock frequency controled by control register.

Control Register	Master Clock Frequency	I2C Clock frequency
0	10 MHz	1 MHz
1	5 MHz	500 kHz
2	2.5 MHz	250 kHz
3	1.25 MHz	125 kHz
4	630 kHz	62.5 kHz
5	312 kHz	31.3 kHz
6	156 kHz	15.6 kHz

---

-- PatrickRobbe - 18 Oct 2005

Create a master for C. Pailler to test interrupt. Enable read is directed to lint1 and checksum error to lint2. The corresponding firmware is pof.

Test a PC with 3 masters (pc-dalmagne). It works after modification of emitter part of master firmware.

---

-- PatrickRobbe - 27 Oct 2005

Program masters # 1, 2, 3, 4, 5, 6 with firmware 21102005 and mezzanine #111 with firmware 0609.

---

-- PatrickRobbe - 03 Nov 2005

Program master #13 with firmware 21102005, and mezzanines #105, #103 and #113 with firmware 0311 (with possibility to switch LEDs off writing 0x80 in register 4).

Solder Mezzanines #105, and #103 with resistances ~20 kOhms, and give to Clara the mezzanines for Ken[#105] (and for LAPP[#103]).

Leave 2 masters for Clara (#3 and #6), and leave master #1 for LAPP.

---

-- PatrickRobbe - 08 Nov 2005

Results of the 6 master test:

We run an application which starts several threads in parallel, each of them executing the same action but using a different master (a different board or a different port on the same board). The time is computed before the start of the first thread and the end of the last one.

Test #1: 100000 Read/Write on the register #3 of the internal slave of the master

Number of Masters used	Time (s)
1 Master	2.6
4 Masters on the same board	4
6 Masters all on a different board	4.7
24 Masters (4 * 6)	16.5

Test #2: 10000 Read/Write of 25 I2C words using the internal slave of the master to a unassigned address:

Number of Masters used	Time (s)
1 Master	5.4
4 Masters on the same board	5.6
6 Masters all on a different board	5.6
24 Masters (4 * 6)	9.8

We observed that to obtain a better sharing of CPU time spent between different masters (in particular when we wait for the enable read and enable write bits) if we introduce the statement "Sleep(0)" (for Windows, no solution for Linux yet) in the ReceiverFIFORead and EmitterFIFOWrite functions of the SpecsLib.