RICH Level 0 operation

-- Main.sean - 03 Aug 2007

The latest production level project in PIT is PVSS3.6, R2DAQL0 _v3_0_0

Starting the project

  • Log in to r2daq01w and r2daq02w

  • run StartL0.vbs from the G:/RICH/Oper folder r2daq02w. Press OK for all the pop up boxes that appear. Once this has run there should be 1 server called DNS.exe, 1 SPEcs server and 7 RICH_L0_DimServers running.

  • run StartL0.vbs from the desktop on r2daq01w. Press OK for all the pop up boxes that appear. Once this has run there should be 1 SPEcs server and 11 RICH_L0_DimServers running.

  • The FSM should start automatically (see otherwise "Starting the FSM")

  • run "device editor and navigator panel" from the PVSS console

  • go to "view"

  • one can navigate to A and C side from here, down to top level FSM for each side, each column and the panels relevant to each board.

  • Go to the PVSS3.6 console, check that all PVSS00DIM managers are running.

The rest of this manual requires that the LV_Lo and LV_Hi are on, and that the LV regulators are powered up. See Antonis for the instructions.

Configuring L0 boards

  • Open the Device Editor and Navigator from the PVSS console
  • On the FSM tab, right click on R2DAQL0 and click view
  • Click on the lock icon in the panel named R2DAQL0. Click 'take'
  • Click on the state (currently should be NOT_READY) underneath 'System' in the panel which is named "R2DAQL0:R2DAQL0:manager1". Click 'configure'.
  • Click OK to configure in 'PHYSICS' mode (Here, PHYSICS mode is ALICE mode by default).
  • To Configure in LHCb mode instead type 'LHCB' into the pop up box instead of 'PHYSICS'
  • any errors can be recovered and then configuration tried again. Use 'recover' in preference to 'reset' if the power is on.
  • Once the boards move to "ready", they will take data.
  • To see the PINT test pattern on all chips on a column, double click on the panel for the side of the RICH that is of interest in the FSM panel window. Navigate to the column of interest click the pint test pattern button in the FSM panel for the column S1. You will need to click 'GetPint Defaults' to activate this button. The PINT defaults will put the boards into LHCb mode.
  • To re-set Alice mode, click the relevant button. Again you will need to click 'GetPint Defaults' to activate this button.
  • To set a special test pattern of lines of pixels on each of the pixel chips, click the chips to activate on the RHS of the FSM panel and then "Set". Alternatively, just click test all to switch it on for all chips. The odin needs to be 'timed in' for this to work. The Odin settings are also on the twiki.

Panels The Top Level L0 panel

  • Open the Device Editor and Navigator from the PVSS console
  • On the FSM tab, right click on R2DAQL0 and click view

You can switch on a well timed in pixel test pattern for all boards in rich 2, there are 3 different test pixel patterns:

  • There is a drop down box to select the relevant pattern, one which turns on the corner pixels (0,0), (0,255) (32,0) (32,255), one which puts horizontal lines of test pixels across the chip, and one which displays a clock face on each HPD.

Switch OFF

No special configuration is needed before switching off.

Advanced Configuration

To access advanced confiuration for an L0 board, double click on the L0 board to configure in the FSM panel for Column 1. The relevant chips on the board can be configured by single clicking on the buttons associated to that chip in the new panel that pops up.

HPDs

The most notable thing one might want to look at is the HPD test pattern, this can be set by clicking on the "HPD0" and "HPD1" buttons.

Click "Apply Test Mask" in the new panel. This puts a few lines of test pixels. note :The test pixels will only be seen in data if time alignment and/or odin is configured properly to see them.

It is also possible to manually mask and test individual pixels if this is useful. Click on the pixel to mask in the green representation of the pixel chip, left. The masking and testing is done alice pixel by alice pixel. Access the sub pixel to mask in the Sub Pixel menu, click the check box and then remember to click OK to apply the change. This button may be greyed out if the special test pattern is on.

The entire chip can be masked or tested by clicking the buttons bottom left. This button also may be greyed out if the special test pattern is on.

Thresholds can be changed by selecting the top left combi box and moving to the PRE_Vth selection. Write the new threshold value (integer setting) into the "Value (dec)" box. Click "Write". A higher threshold is gained by writing a lower PRE_VTH.

PINT

The pint config & reset registers can be set from here, as can the strobe and test pulse registers. Write "1" (or better, "385") into the config register to generate the pint test pattern.

The coarse timing of the test pulses can also be changed from here.

TTCrx

For test pulse runs, one might want to change the fine timing of the test pulse. Change Clock Des 2.

For fine timing with respect to the external light source (laser, cherenkov radiation particles) Change Clock Des 2 and TTCrx coarse delay.

Error recovery. (assumes basic knowledge of PVSS)

In the FSM, the boards may enter error state for several reasons.

Wrong recipe

If you are using a unique recipe, try configuring again with the run_mode =PHYSICS

External programs not running or hung

Procedure - check DNS server is running as a DOS window in te task bar.

Check RICHL0_Dim server is running as a DOS window in the task bar.

These can be started by running S3.vbs form the desk top

SPECS has hung

Close SPECS server and DIM server. Restart them by running s3.vbs from the desktop.

If this fails, close the DIM server but not the specs server. Power off the column, power on the column and then run s3.vbs again. Reconfigure.

PVSS managers failed

The PVSS00Dim manager may not be running,

Open a PVSS console, look near the bottom of the list of managers for the manager PVSS00DIM with the parameters

-dim_dp_config RICHL0 -dim_dns_node -num 9

PVSS managers extremely slow to register

Sometimes it can take up to 30 minutes after starting this manager for the services to be properly registered with PVSS. The only known solution is to wait.

In the ssb2 the DIMDNSNODE is lbriwico01

Check these parameters and start the manager.

SPECS is in a state where errors regarding the clock frequency appear in the SpecsServer

Only known solution is to power cycle the computer .

Time out

If the error is none of the above, it might be a time out error. Try configuring only 1 board at a time.

Starting the FSM

  • run "device editor and navigator panel" from the PVSS console

  • go to FSM tab

  • start/restart the FSM

  • left click then right click on R2DAQL0

Installing the project safely

It is safest to start from scratch
- instructions for Rich 2

  • Make a new project called R2DAQL0. The project directory should be in the L:\PVSS folder in the pit. Call it R2DAQL0.
  • This project should be distributed, but to protect it while installing any components you should edit the config file to prevent other systems in the distributed network from connecting.
  • From the PVSS console, select the project R2DAQL0, edit the config file. Add distributed = 0 to the config file.
  • Completely stop the project and copy the fwInstallation panels into the project directory.
  • Start the project and run the fwInstallation panel
  • Install fwCore, fwDIM, lbFSMDomains, fwSPECS, fwConfingurationDB, fwHW, fwFSMConfDB
  • Restart the project and install the latest lbRICH_L0 component.
  • Restart the project and run the script SetupRICH2 from the console.
  • ...Go get a cup of coffee/ tea or more likely you have time for both.
  • Stop the project
  • Edit the config file to read distributed =1
  • Under distributed =1 type
    pmonPort = 27500
    dataPort = 27501
    eventPort = 27502
  • At the end of the config file, add [dist]
    distPort = 27510
  • Project now installed
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Topic revision: r5 - 2007-11-12 - SeanBrisbane
 
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