L0 Operational Information

Please note that correct operation of the L0 boards (configuration, readout etc.) requires the clock signal from the TFC system to be present.

You want to start the DNS, Specs and Dim server R2DAQ02w and R2DAQ01w by logging on to these PCs and starting the S3forR2DAQ01W_C_side.vbs or S3forR2DAQ02W_A_side.vbs from G:\rich\pvss\fwComponents_R2DAQ1\090507\bin[\a-side]. When prompted for the DIM_DNS_NODE, leave it as R2DAQ01W. At the stage of a dialog box appearing and asking for a column number for PILOT calibration, pause. Then go to the LV project on r2dcs01w and set the L0BoardCtrl FSM state to READY. Switch back to PC r2daq01w, close the SPECS server, and then click OK/Run in any remaining dialogs that appear from the S3...vbs script that was started earlier (entering no column number for PILOT calibration) and wait until the script has finished and windows have finished opening. Make sure the FSM of the appropriate column in the R2DAQL0 project is in the NOT_READY state (an FSM reset might be necessary), then CONFIGURE. All L0 boards will be in ALICE mode by default at this point.

The main operation of L0 PVSS is by running the project R2DAQL0_v2 from the r2daq01w pc. Start this project on this PC, run the device editor & navigator and start the FSM. Open the column you wish to configure and click configure.

NOTE: if one of the SPECS masters (which have 4 channels per card) is not working correctly, then the column numbering scheme in the L0 project may differ from that in the LV project, e.g. column C5 is referred to in the L0 project as C1 because the addresses have shifted by 4 (= the number of ports per SPECS master)

To power down, close the DIM servers on r2daq01w and r2daq02w. Then run the vbs script again, so as to re-open the SPECS servers. On r2dcs01w, set to OFF the L0BoardCtrl FSM, followed by setting the column's FSM to OFF so that the LV channels are switched off.

Pixel chip test pulses (test rows)

Settings that enabled test rows in the SSB2 on 25/4/7 were (assuming the test flag has been set for some pixels):
  • PINT Calibration/test pulse register: 11548451 (i.e. N_start=35, N_stop=55, N_trig=176)
  • Pixel chip delay_control DAC: 79
  • ODIN Calib. trigger A selected in main panel
  • ODIN Calib. trigger delay A set to 205 (and Calib. trigger A window = 3)
  • ODIN L0 Latency set to 176
Other settings that were found to work in the SSB2 on 27/4/7 are (all with delay_control=79 and with ODIN L0 latency set to 176):
  • N_start=34, N_stop=54, N_trig=176, ODIN Calib. trigger delay A=205, trig. A window=3
  • N_start=4, N_stop=24, N_trig=176, ODIN Calib. trigger delay A=175, trig. A window=0
  • N_start=5, N_stop=25, N_trig=176, ODIN Calib. trigger delay A=176, trig. A window=0
  • N_start=5, N_stop=15, N_trig=176, ODIN Calib. trigger delay A=176, trig. A window=0
Suitable values of TTCrx fine delay 2 were in the range 90-210 (* 104.17ps). Although N_trig settings are given above, it is not known whether the events were correctly labelled as calibration events (the PINT documentation in fact indicates that the N_trig value should be 176-2=174)

On 8th & 9th May, test rows were seen at the pit, with the following settings (different N_start & N_stop values were set on each L0 board):

  • Pixel chip DAC 43 ("delay_control") = 79
  • PINT N_start = {3...10}, N_stop = {13...20}. N_trig=176
  • ODIN Calib. trigger delay A=172, window=0 (calib. trig. A offset should not matter, and worked with values of 128 & 256)
  • ODIN L0 latency=176
  • ODIN L0 gap length = 1

On 9th May, after another power cycle, the following settings allowed us to see test rows on all HPDs:

  • N_{start,stop,trig} = 5,15,176
  • Pixel chip delay_control DAC = 79
  • ODIN Calib. trigger delay A=170, window=0; ODIN L0 latency = 176; ODIN L0 gap length = 1

On 10th May, with columns 1 and 8 on RICH2 C side, timings that were found to work were:

  • N_{start,stop,trig} = 10,20,176
  • Pixel chip delay_control DAC = 79
  • ODIN Calib. trigger delay A=176 or 175, window=0, ODIN L0 latency=176; ODIN L0 gap length=1

On 10th May, with column 2 on R2C side, timing that was found to work was

  • N_{start,stop,trg} = 10,18,176
  • PINT_config = 11539466 (=> N_{start,stop,trig)=10,20,176 & ODIN Calib. trig. delay=176 gave some test pulses, but at low efficiency, on R2C col. 2
  • PINT_config = > N_{start,stop,trig)=11,21,176 & ODIN Calib. trig. delay=176 gave higher (85-100%) efficiency, on R2C col. 2.
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Topic revision: r5 - 2007-10-29 - StephenWotton
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