The information provided here complements the information found in

Useful links
PDMDB motherboard Handbook
PDMDB TCM/DTM plug-ins Handbook
PDMDB production test data Oxford test summary pages
PDMDB inventory (CERN) List of PDMDBs shiped to CERN

The RICH PDMDB provides the configuration and data interface between the elementary cells and the LHCb readout system (or miniDAQ or RichMuDaq). The hardware is based on 3 Xilinx Kintex7 FPGAs that capture the FE data from the digital CLARO outputs and forward them to the readout sytstem via 3 DTM (Data Transmission Module) plug-ins that each implement two GBT links. The PDMDB is controlled through a TCM (Trigger and Control Module) plug-in that implements the LHCb configuration and fast control interface over one bi-directional GBT link.

ALERT!The sketch below illustrates the R-type PDMDB. The H-type PDMDB has two DTMs and two FPGAs (FPGA.1 and DTM.1 are removed and the MAPMT signals redistributed).

ALERT!The sketch does not correctly reflect the actual order of the FPGAs on the JTAG chain. The order is TAP→FPGA.2→FPGA.1→FPGA.0→TAP. The order is not the same on prototype boards.



Note that the EC index is the PDMDB PCB ordering. The mapping to the physical ECs must take account of the relative rotation of the two PDMDBs on the PDM.

Board type PDMDB EC DTM
V1 (prototype) View View View
R1 (R-type production) View View View
H1 (H-type production) View View View

Synchronisation and timing

The latest PDMDB hardware provides both 40MHz and 160MHz synchronous clocks to the FPGA. This greatly simplifies the link synchronisation of the data transmission links. For the synchronisation with GBTX.0, the FPGA serialiser 40MHz clock needs only to be delayed by a fixed amount relative to the input 40MHz clock and the serialisers reset synchronously. This can be done on power-up reset of the FPGA using fixed internal shift-register delays so no external tuning is required. However, it has not yet been demonstrated that the same delay can be used for all FPGAs on all boards. For synchronisation with GBTX.1, exactly the same settings can be used but the correct phase of its 40MHz input reference clock must be found. Empirically, setting ps.0.coarse-delay register to 15 appears to give good results.

The diagram below shows the clock distribution starting from the reference clock (shown for the muDAQ environment but the principle is the same for the SOL40/TEL40 or miniDAQ environment). Red arrows indicate serial links which carry both clock and data. CDR techniques are used to recover the clock at the receiver.

PDMDB clocks


The DTM GBTX settings are based on the xPLL-bypassed configuration.

One prototype DTM (#19) appears to require the e-group phase-aligner PLL to be reset after configuration. This is likely to be because GBTX0 has been e-fused. A reset sequence similar to that recommended for e-fused TCMs is therefore advisable for this DTM. It is not recommended to do this for production DTMs since the GBTXs are not efused and the correct sequence of resets is issued by the startup FSM.

The phase of the data transmission e-links must also be adjusted. Empirically, a value of 5 in the eport.pa.*.0.phase and eport.pa.*.4.phase gives good results for all e-links with no bitflips seen. The strategy may need to be reviewed in the light of the production testing if significant variations are seen.

In the muDAQ environment, the above settings are used identically on all DTMs.

ALERT! There seems to be some numbering confusion for the uplinks used in widebus mode. In 320Mbs mode, the manual names the uplinks as dIO1,5,9,13 for groups 5 and 6 (the other groups use dOut0,4...). However, dIO1 is enabled using bit 0 in the enable and train configuration registers but bit 1 is used for the terminations register.


Minimal fuse settings 1.
Name Value Note
watchdog.startup-timeout-enable 0x1
watchdog.enable 0x1
xpll.frequency-trim 0x5d 2.
xpll.control-override 0x1
xpll.gm-select 0xa
cm.refclk.select 0x1
efuse.update.enable 0x1
deserialiser.resistor 0xd
rx.frequency-detector 0x2
rx.phase-detector 0x4
rx.valid-headers 0xf
rx.max-invalid-headers 0x4
rx.min-valid-headers 0x8
rx.select-i1 0x2
rx.switch.0 0x1
rx.switch.1 0x1
rx.switch.2 0x1
tx.switch.0 0x1
tx.switch.1 0x1
tx.switch.2 0x1
serialiser.lock-time 0x6
serialiser.unlock-time 0x3
serialiser.current 0x8
serialiser.resistor 0x2
tx.select-positive-edge 0x1
eport.pa.ec.config 0xd 3.
eport.pa.ec.enable 0x1 3.
eport.pa.ec.termination 0x1 3.
eport.pa.coarse-lock 0x1 3.


  1. For e-fused GBTXs, after power up, the remaining registers must be loaded and some GBTX functions must be reset following the recommendation below.
  2. This value is not critical. The CDR appears to lock even for extreme values of this setting.
  3. It is probably convenient also that the EC (SCA) e-port also comes alive at power up.

The GBTX register descriptions are summarised here for reference.

Here is the resulting list of non-zero bytes to be e-fused:

[027,01b] 28
[029,01d] 15
[030,01e] 15
[031,01f] 15
[032,020] 66
[034,022] 0D
[035,023] 42
[037,025] 0F
[038,026] 04
[039,027] 08
[041,029] 20
[046,02e] 15
[047,02f] 15
[048,030] 15
[050,032] 07
[052,034] 38
[231,0e7] DD
[232,0e8] 0D
[233,0e9] 70
[244,0f4] 38
[248,0f8] 07
[273,111] 20
[281,119] 15
[313,139] 5D
[314,13a] 5D
[315,13b] 5D
[316,13c] AA
[317,13d] 0A
[318,13e] 07

With the above settings, the link appears to automatically re-establish if the master link is temporarily down.

IDEA! Only registers that differ from 0 are listed. The set is based on the xPLL-bypassed (VCXO) configuration.

ALERT! Once efuse.update.enable is programmed, configuration will no longer pause at pauseForConfig and all other registers will contain 0 until programmed through the fibre or or I2C interface.

Production TCMs are factory-configured to default to the fibre configuration interface. When used in the standard way, the I2C interface is inactive.

The following steps are recommended to complete the configuration of e-fused master GBTXs:

  1. Power up. The master link and EC (SCA) e-port should come up automatically.
  2. At this point the SCA chip should be accessible and could be set up and used if needed (e.g. for temperature monitoring).
  3. Write GBTX registers to disable the watchdog and timeout features (without touching other registers).
  4. Load the full configuration file (which must have the watchdog and timeout registers still disabled and must not modify the e-fused registers.)
  5. Write GBTX registers to assert and then deassert the e-port phase aligner resets.
  6. Write GBTX registers to assert and deassert the phase shifter PLL and DLLs respecting the ordering and the required locking times.
  7. Write GBTX registers to re-enable the timeout and watchdog.
  8. Continue with system configuration including SCA set-up if not already done.

The interplay between the watchdog and timeout logic may cause the soft configuration to be lost (if the master link loses lock for example) and under these circumstances will need to be reconfigured from step 3. It may not happen in practice but it is a possibility. It can be detected by reading a GBTX register that contains zero but should be non-zero.

The above does not apply to the DTMs. These GBTXs can simply be configured as we do now.


See RichPdmdbProductionTesting.


A list of production PDMDBs delivered to CERN can be found here.

There are also a number of prototype boards in circulation. The lists of these are tabulated below. The Excel files are convenient for sorting etc. These tables are for prototype and pre-production modules only.

.xlsx .xlsx .xlsx
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Topic revision: r36 - 2020-05-11 - StephenWotton
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