Three testing phases:

  1. Viisual inspection and basic powering test using Philip's board connected to testing edge connector.
  2. Basic set-up of board.
  3. Statistical tests.

ALERT!Testing hardware/software/firmware needs to compatible with both R-type and H-type modules.

ALERT!To be decided where/when to burn TCM e-fuses but will most likely be during TCM testing before they are mounted on the PDMDB.

Phase 1

Cambridge. Before mounting of TCMs and DTMs. Use power testing board with microcontroller.

  • Check that excessive current is not drawn.
  • Check all voltage levels within acceptable limits.
  • Check FPGA JTAG?
  • Mount TCM's DTMs
  • Recheck voltages. Check currents.

Phase 2

Oxford/Bucharest/(Cambridge).

The aim of this is to quickly establish that the basic functionality is good.

  • Couple to Rui's board
  • Check that excessive current is not drawn.
  • Read barcode.
  • Basic board and master link set-up (configureMasterLink())
    • Establish master link
    • Check lock
    • Read master GBTX serial number (in e-fuses)
  • SCA setup (setupSca())
    • Establish and check link with SCA
  • Record PDMDB power sense ADC channels.
  • FPGA configuration (programFpga()).
    • Load bitstream. Readback of bitstream is not needed since succesful FPGA startup requires successful CRC check.
    • Record IDs, temperature and voltages.
  • DTM (configureDtm())
    • Write and verify configuration with SCA I2C.
    • Check GBTX status (lock, power-up FSM).
  • GT link tests (doEyeScan())
    • Record TCM eye diagram
    • Record DTM eye diagrams
  • E-link tests (doPhaseScan()).
    • Do phase scan tuning. This checks also FPGA I2C and TCM downlinks.
  • ADC/DAC (getAdc())
    • Loopback DAC to ADC inputs via Rui's board and check with muDaq or
    • Use combination of Rui's board and muDaq to check.
    • Set a voltage and check that the value is reasonable.
    • One ADC channel measures the voltage across a precision resistor for current source calibration.
    • NB: take care when configuring SCA ADC current source.
  • EC GPIOs
    • Either loop them back through Rui's board and perform tests via muDaq or
    • use combination of muDaq and Rui's board to read and write.
  • SPI
    • This requires Rui's board to act as a simple SPI slave.
    • Check each SPI slave select is correctly asserted. Send captured SS pattern as SPI data.
    • Check the function of write enable and feb enables (can be done during GPIO checks).
    • SCA-SPI master sends pattern to MOSI, slave loops back to MISO. Check the pattern agrees.
  • EC MAPMT IOs
    • Shift PRBS through chain of looped back IOs
    • Implement e.g. LFSR in FPGA firmware and counters to count bit errors.
    • Use I2C slave implementation monitor through master link.
  • Other
    • Check function of FPGA power enable GPIO.

Phase 3

Oxford/Bucharest/(Cambridge).

In this phase, the reliability is tested by repeated cycles of as many features as possible. It is possible that BER of the data links might have to be deferred to CERN because the muDAQ may not have the necessary capability.

  • Repeat GBTX configuration write/verify cycle.
  • Repeat FPGA program/verify cycle
  • Repeat SPI write verify cycle.
  • Repeat MAPMT IO tests

Bookkeeping

A test report should be produced for each DB. Should be written automatically by testing software in a form that is easy to upload to a database. Excel tab-delimited may be suitable as it can also be easily corrected in Excel before upload. Barcode reader will be invaluable. Maybe make a simple web form to allow seeding of records with barcodes read using a smartphone or other barcode reader.

To be recorded:

  • PDMDB barcode (key to the entry)
  • Cross-references to TCM and DTM barcodes
  • Master GBTX e-fused serial number
  • FPGA DNA
  • Pass/fail status of each test
  • Measured voltages
  • Statistical error counters
  • Statistical datasets of ADC measurements?
  • Cross references to external data (e.g. eye diagrams)

Logistics

PDMDBs, TCMs and DTMs delivered to testing facility from Cambridge (fully assembled or separate?). Shipment direct to CERN from test facility or back to Cambridge first? Need to prepare packaging. Must keep shipping records.

Tester commands

See RichPdmdbOxTesterCommands.

-- StephenWotton - 2018-11-23

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Topic revision: r4 - 2019-04-15 - StephenWotton
 
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