RICH testbeam with miniDAQ

Some documents with additional information can be found here:

DAQ PC

The current configuration is to use a single PC (the miniDAQ server) for all DAQ and controls functions. The configuration is very fluid at the moment.

The normal miniDAQ login for DAQ is "lhcb".

PC Login Usage
lbrichmd1 lhcb miniDAQ server
pclbrich02   Firmware development

WinCC

Package Server Client Location Top
TFC lbrichmd1 CCPC1 ~/projects/RichAMC40_4aa
DAQ lbrichmd1 CCPC2 ~/projects/RichAMC40_24Links
RICH lbrichmd1 CCPC1 ~/projects/RichAMC40_4aa

RICH PDM

The RICH front end module is the PDM. A fully equipped PDM comprises 4 elementary cells (16 MaPMTs) and two PDMDB readout boards. All DAQ and control functions are mediated by the PDMDB through the master link connected to the SOL40. Each PDMDB also carries three DTM plug-in modules each of which drives two GBT links. A full PDM therefore has two master links and 12 data links.

The PDM raw power input is about 7A and can be between 5V and 7V. A secondary 2.5V is derived from the raw input using an additional regulator.

A fully loaded PDMDB draws about 2A before the FPGAs are programmed. This rises to about 3.5A with all FPGAs programmed.

GBTX settings

A Java GUI can be used to prepare the GBTX settings files although they can also be edited by hand. The GUI can be found at ~/programmerv2.20160801/ and started with the command:

java -jar programmerv2.20160801.jar

or

gbtx-programmer

from any console as lhcb.

The tool is intended to be used with the CERN USB dongle but we have found this to be very unreliable (device not recognised or only intermittently recognised on most systems) but to use the GUI you must still click on 'Write GBTX" before using the Export option to generate a file containing the settings. This file can then be written to the GBTX using JRichTBTrigger as previously described. It is recommended to Import an existing known good settings file before changing and exporting any settings.

PDMDB

Installation and cabling

Note that PDMDB1 is inverted wrt PDMDB0. For PDMDB0 DTM0 is at the top and for PDMDB1 it is at the bottom.

Fibre Usage
PDMDB0
1A.11 (pink) DTM0.GBTX0
1A.02 (orange) DTM0.GBTX1
1A.03 (green) DTM1.GBTX0
1A.05 (grey) DTM1.GBTX1
1A.01 (blue) DTM2.GBTX0
1A.04 (brown) DTM2.GBTX1
1B.12 (cyan,top) TCMRx
1A.12 (cyan,bot) TCMTx
PDMDB1
07 DTM0.GBTX0
09 DTM0.GBTX1
11 DTM1.GBTX0
12 DTM1.GBTX1
02 DTM2.GBTX0
01 DTM2.GBTX1
1B. (yellow,bot) TCMRx
1A. (yellow,top) TCMTx

The normal way of programming the FPGAs is now via the miniDAQ. For this, JTAG loopback connectors must be installed on the PDMDB boards.

The bootstrapping of the master link GBTX is done via an external I2C master. This function is served by the trigger board via cables connected from the Tengja board to the PDMDB. The trigger board connections can be found in the JRichTBTrigger topic.

The PDMDBs require two power supplies. A raw power supply of about 6V and a regulated 2.5V supply. For the test setup the 2.5V is integrated into the power cables.

Configuration

This is not a simple operation at present.

Once the master link is configured, the control functions for the elementary cells should be usable immediately. After power-up the SCA should be initialised before any other control function is used. There is an Initialise button on the RICH panel to do this. It activates all the required SCA interfaces (I2C, GPIO, JTAG, ADC, DAC). At this point it is possible to configure the CLAROs by clicking the appropriate button on the panel. In general, when clicking buttons in the panel, check that the action has completed successfully (output in window on panel) before proceeding with the next operation.

The next step should be to configure the DTM modules. The DTMs are in pairs - DTM0 must always be configured before DTM1.

The FPGAs can now be configured.

The next step is to align the links. The master link should be aligned first, then the data links.

Now the PDM is ready to receive TFC commands and to send data.

CLARO configuration

Pre-prepared sets of configuration data are loaded into the CLARO chips using buttons on the RICH panel. The data files (one per PDMDB) can be prepared using the JRichXmlToCLARO Java GUI. It can be found in ~/RICHECKIT/ and can be started with the command

java -Djava.library.path=. -jar JRichXmlToCLARO.jar

or

claro-configurator

from any console as lhcb.

The GUI contains a single Convert button that prepares the files using the settings managed by the JRichEcConfigurator program. For convenience JRichEcConfigurator can be started from the Main menu. For the process to work, JRichEcConfigurator must have exactly 8 DBs assigned to 4 ECs. The EC names are arbitrary. However, the DB names dictate the order in which the configuration data is written to the output files therefore it is recommended to follow a scheme such as the one in the table below:

EC name DB(AB) name DB(CD) name
EC-Top 1 8
EC-MT 2 7
EC-MB 3 6
EC-Bot 4 5

The numbering reflects the fact that the CD PDMDB is inverted compared to the AB PDMDB.

MAC addresses

Device IP name MAC Login
IP switch lbrichps1 00:92:58:00:d3:54 admin
miniDAQ lbrichmd1 34:17:eb:cf:21:4a

Set up the system from scratch

In the following there are the steps to set up the miniDAQ and PDMDB system in order to take data.

Power cycle the PDMDB and the CCPC

12V for the minidaq and 5.12V (not incidentally) are controlled via LabView from pclbtb06; it's a windows10 pc, so

remotedesktop via cernts, user lhcbrich

If the labview VIs are not open, double-click on

C:\Users\lhcbrich\Downloads\4-slot TTi control/Tsx3510p.lib

and open the 5V and 12V VIs.

The trigger board and PDMDB power is supplied from the CAEN crate. 3.3V for the trigger board and 6V for the PDMDBs. The voltages are controlled from the DCS panel.

[Controlling the old miniDAQ power supply is done by opening a browser to lhcbpower and switch on Power1. This power supply is not used in the current configuration.]

Connect to the CCPC

Open a terminal on lhcbrich@pclbrich02 and type

ssh root@ccpc1

to open a connection to the CCPC

Load the miniDAQ firmware

on lhcbrich@pclbrich02:

Open Quartus 15.1.2 (shortcut on the desktop). Go to File->Recent files and select the file with name /home/Firmware/local_quartus/mini_daq_firmware.sof. The programmer window opens. Before uploading the firmware, kill the GbtServer. To upload the firmware click Start button. Close the programmer window.

Start the ecs driver

On the ccpc1 shell, type

ecsdrv

The terminal will print some messages. At this stage it is important to check that the lines under GetBar0 and GetBar2 start with "Base Address". If not, the ccpc1 must first be rebooted (reboot), then you have to open a new ssh connection to it and then try again typing the ecsdrv command. Normally the second shot is fine.

Start the GBT Server

On the ccpc1 terminal type

GbtServ -debug:0 -nodaemon -level:7 &

Start the WinCC project

Open the WinCC Project Administrator, start the MiniDAQRich_v4r2 project. Go to JCOP Framework->Device Editor and Navigator, select the FSM tab. Click the Start/Restart all button and then right click on the MiniDAQ top partition and select view. Take the FSM. Click on MiniDAQ expert button. First click on the Restart ctrl managers button and check there is the green light instead of the orange one. If the ctrl managers are ok, then click on the test system button and check again there is the green light. If not, restart again the Ctrl managers.

The MEP is in the offline mode, in order to restart it: open a terminal and type:

cd /home/Packages/git/lhcb-daq

Initialize the system

On a richtbuser@lbrichtb terminal type

tb-trigger

In the Java JRichTBTrigger GUI click on the Extra drop down menu and select GBTX I2C. The GBTX I2C Java GUI opens. Click the Read button on the PDMDB0 until you see random values (not all zero). Then click Write and choose the master3g.gbt file. Then click Read. Do the same on the PDMDB1. You should see the same numbers as in the screenshot below.

* GBTX_IC2.png:
GBTX_IC2.png

Then move to the WinCC TopV4 panel and click on the Initialize button at the top Check on the CCPC terminal that there are no errors.

Tick the fast mode option. Click Program all the GBTs button. All the GBTs button should become green. If not try to click on the red single Program GBT button(s).

Click on the Check GBTs button.

Do this for both the PDMDB0 and the PDMDB1.

On the GBT client panel (it should open by itself), select GBT in the radio menu go tho the JTAG tab.

For the PDMDB0

PC: CCPC1
GBT ID: 3
SCA ID: 0

* GbTClientJTAG.png:
GbTClientJTAG.png

Click on Activate channel, JTAG Reset, DR scan buttons.

For the PDMDB1

PC: CCPC1
GBT ID: 4
SCA ID: 0

Click on Activate channel, JTAG Reset, DR scan buttons.

Load the PDMDB firmware

On the CCPC terminal kill the GBTServer.

To upload the firmware use the script:

./LoadFirmware.sh  3
./LoadFirmware.sh  4

Check that the current drawn by each PDMDB is ~2.6 A Restart the GBTServer

Check on the WincCC TopV4 panel that the Ctrl Manager is green, if not restart the Ctrl manager

Phase alignment

Use the TopV4 panel and click on the PDMDB0 button. Tick the Ignore TFC, Force SYNC and Force TP boxes to the right of the panel. Program each FPGA waiting for a successful message in the box at the bottom of the panel.

Now open the TELL40 partition in the FSM (go to the Device Editor Navigator, FSM tab and right click on the TELL40 partition), select the Memory monitoring tab, move to Loop Memory at the top. Select the fiber corresponding to the DTM (6,7 for DTM0, 8,9 for DTM1 and 10,11 for DTM2 for PDMDB0 and 12,13 for DTM0, 14,15 for DTM1 and 16,17 for DTM2 for PDMDB1). Click on the Program GBT0 button (the ones to the left) on the PDMDB panel and check if you see lines with 9F in the Memory monitoring panel. Repeat the procedure for DTM0, DTM1 and DTM2 and for the 2 PDMDB separately until you see lines with 9F.

Check that the write signal staus is green and that the displayed number of the fibre is changing when you change it. If not check the status of the Ctrl Manager in the TopV4 panel. If red, restart the Ctrl manager.

Once you have 9F on every fibre, deselect loop memory.

Untick Ignore TFC, Force SYNC and Force TP in the TopV4 panel and then click on Configure FPGA0, Configure FPGA1, Configure FPGA2.

Click and select Start run from the FSM of the MiniDAQ TOP.

Now go back to the TELL40 partition in the FSM (it should be open, if not go to the Device Editor Navigator, FSM tab and right click on the TELL40 partition), select the Decoding tab. Check if the links are green. For the links which are blue, change the corresponding config files (PDMDB(0,1)FPGA(0,1,2)iserdes.txt): change the line 2200 from 00 -> 03 or from 03 -> 00.

On the TopV4 panel, click on the corresponding ConfigureFPGAx button.

Start the run from the FSM and check again in the decoding tab the startus of the links.

Threshold scan

How to run and analyze a threshold scan

DAC scan

How to run and analyze a DAC scan

Trigger delay scan

How to run a trigger delay scan

BXID scan

How to run a BXID scan

If the pclbrich02 screen got stuck

Using a terminal of another workstation connect to the machine using:

ssh -Y lbrich@pclbrich02

Then type the command:

killall -9 gnome-shell

KRDC sessions

MiniDAQ1: pclbrich02:5902

MiniDAQ2 (sysLab): lbminidaq2-13:5903

MiniDAQ2 (CHARM): lbminidaq2-06:5902

How to run the data quality monitoring

Move to /home/Packages/Dqmp/

and type:

source startDQMP.sh

To compile the RICH version move to:

/home/Packages/Dqmp/Dqmp40/qtbeam/

and type:

make clean make

To run in standalone mode type:

$DQMP/Detector/rich -o

-- StephenWotton - 2016-09-08

Topic attachments
I Attachment History Action Size Date Who Comment
PNGpng GBTX_IC2.png r1 manage 21.7 K 2017-05-16 - 10:16 LhcbTestbeamSupportService  
PNGpng GbTClientJTAG.png r1 manage 40.7 K 2017-05-16 - 10:32 LhcbTestbeamSupportService  
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Topic revision: r31 - 2017-10-01 - RobertaCardinale
 
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