Hardware

The trigger board outputs and gate inputs use LVDS differential signalling. One of the trigger outputs is sent to the beam telescope trigger input via an LVDS to LVCMOS translator. Attention must be paid to the correct termination of this signal. If the translator output is using 1V8 LVCMOS then a simple 50 Ohm termination to ground is needed at the telescope SPIDR board. If the translator output is 3V3 LVCMOS a 22 Ohm series + 27 Ohm parallel termination is required so that the signal is compatible with the 1.8V input level of the SPIDR FPGA.

Level translator
Input 32 (blue to white)
Output BUSY (label on the box)

DAQ

The trigger sent from the RICH to the VELO telescope introduces a timestamp into the VELO data that is used to correlate the VELO hits with the RICH events. To ensure that this mechanism works it is important that both the telescope and RICH see the same number of triggers. To do this, make sure that both detectors are started and stopped between SPS spills when there are no triggers arriving. At the end of every run (and preferably after every spill) check that the telescope and RICH trigger counters agree.
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Topic revision: r1 - 2017-05-30 - LhcbTestbeamSupportService
 
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