Work package: Electronics

WP leader: herve.chanal@cernNOSPAMPLEASE.ch

Scope

Develops, manufactures and fully characterises the PACIFIC ASIC, the motherboard and back-end electronics, incl. the specification, and testing of the cabling and powering. For the series production, the WP will prepare test benches for qualification and reliability tests.

Current main activities

  • Prototypes of the FE boards
  • AMC40 firmware devellopment
  • Full system simulation
  • Production test bench of the FE boards
  • Development of the PACIFIC ASIC (PACIFIC3)
  • Tests of PACIFIC1/2

Issues

  • Spill over (remaining signal in the next event)
  • Components quantities
  • SiPM characteristics unknown
  • Bandwidth needs
  • Zero suppression
  • Back-end decoding
  • Components/optical links quantities
  • Power consumption
  • Power supplies
  • Tight schedule

Contributing institutes

  • Barcelona
  • CERN
  • Clermont-Ferrand
  • EPFL
  • Heidelberg
  • Nikhef
  • Valencia

Next milestones and reviews

planning.png

  • PACIFIC pre-EDR : Q1 2015
  • PACIFIC EDR : EQ3-Q4 2015
  • Electronics EDR: EQ3-Q4 2015
  • PACIFIC EDR : EQ3-Q4 2016
  • Electronics EDR: EQ3-Q4 2016

Further links and material

-- ChanalHerve - 26 Jun 2014

  • planning.png:
Topic attachments
I Attachment History Action Size Date Who Comment
Unknown file formatgan ganttproject.gan r2 r1 manage 14.0 K 2014-11-12 - 17:41 ChanalHerve  
Unknown file formatmpx ganttproject.mpx r1 manage 8.4 K 2014-10-28 - 17:52 ChanalHerve  
PDFpdf ganttproject.pdf r2 r1 manage 3241.8 K 2014-11-12 - 17:41 ChanalHerve  
PNGpng ganttproject.png r3 r2 r1 manage 94.9 K 2014-11-12 - 17:41 ChanalHerve  
PNGpng planning.png r2 r1 manage 33.0 K 2014-09-18 - 16:18 ChanalHerve  
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Topic revision: r8 - 2018-11-27 - BlakeLeverington
 
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