Work package: Electronics

WP leader: herve.chanal@cernNOSPAMPLEASE.ch

Scope

Develops, manufactures and fully characterises the PACIFIC ASIC, the motherboard and back-end electronics, incl. the specification, and testing of the cabling and powering. For the series production, the WP will prepare test benches for qualification and reliability tests.

Current main activities

• Prototypes of the FE boards
• AMC40 firmware devellopment
• Full system simulation
• Production test bench of the FE boards
• Development of the PACIFIC ASIC (PACIFIC3)
• Tests of PACIFIC1/2

Issues

• Spill over (remaining signal in the next event)
• Components quantities
• SiPM characteristics unknown
• Bandwidth needs
• Zero suppression
• Back-end decoding
• Components/optical links quantities
• Power consumption
• Power supplies
• Tight schedule

Contributing institutes

• Barcelona
• CERN
• Clermont-Ferrand
• EPFL
• Heidelberg
• Nikhef
• Valencia

Next milestones and reviews

• PACIFIC pre-EDR : Q1 2015
• PACIFIC EDR : EQ3-Q4 2015
• Electronics EDR: EQ3-Q4 2015
• PACIFIC EDR : EQ3-Q4 2016
• Electronics EDR: EQ3-Q4 2016

Further links and material

• SciFiElectronics page

-- ChanalHerve - 26 Jun 2014

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