-- AntonioPellegrino - 2022-09-14

SciFi Online Scan Runs


Introduction

Several type of calibration runs are carried during the operation of the SciFi detector. Through these runs a number of fundamental parameters (FEE thresholds and time phases, SiPM bias, etc.) are determined and routinely checked.

The overall design of the SciFi scan runs is described in SciFi Scan Specification EDMS Doc. 2703985.

Run Types for the FEE Calibration

The concept of run-type has been introduced to try and categorize systematically the type of scans that are foreseen for the SciFi operation. Concerning the calibration of the FEE, the following run types are foreseen:

  • Run Types
    • FPGA_PRBS_BER_TI_SCAN;
    • PACIFIC_BER_TI_SCAN;
    • BEAM_TI_SCAN;
    • VTTXBIAS_SCAN;
    • LIS_TH_SCAN;
    • CHARGE_TH_SCAN.

More details can be found on the Nikhef Redmine SciFi Control Wiki.

SciFi Online Database and Recipe Creation

Calibration scans make use of the SciFi Online Database for the storage of run settings, calibration results etc. The SciFi database is used to create FSM recipes; as the detector operational parameter change in the course of time, the results of each new calibration are to be stored in the appropriate calibration tables in the SciFi Online Database, from where the recipe-creator software can retrieve them.

Scan Configurations

Once the proper Activity is selected and the SciFi FEE is then configured with the appropriate FSM recipe, the scan is performed, which entails a series of steps, to each one of which the FEE WinCC control software reacts by changing (stepping) some parameters in the detector configuration. Which parameters are stepped and with which value must have previously been defined, through a procedure called Scan Creation, described in detail in Ton's scan twiki and in particular in Ton's documentation about the Scan Creator. This procedure relies on scan configuration files in csv format, which are systematically stored in /group/sf/etc/scanCreatorCollection.

Scan Execution

The actual execution of a scan run requires the cooperation and the synchronization of various FSM components, among the others the top-level ECS, the TFC and the DAQ. The actual execution steps and how they are synchronized are, in truth, rather complex and rather poorly documented. I made an attempt at filling this gap, and summarized the result in the diagram below (although this diagram has been checked by Federico Alessio, it remains largely the work of a non-expert and should therefore be taken with a grain of salt).

Step Run Execution Diagram
Figure 1. Step Run Execution Diagram.

Data Taking and Analysis

This section describes a few rules and conventions that should be implemented when scans are taken and analyzed in order to ensure a certain uniformity among the various implementations. A visual overview of the concept that we have in mind is shown in Figure 1.

Data Taking & Analysis
Figure 2. Overview of the data taking and analysis process of scan runs.

The value of <environmental-var> during commissioning in the SciFi assembly hall at CERN was CframeCommissioning; at the beginning of Run3 (2nd half of 2022) this was changed CavernCommissioning. As the project evolves to next phases, the value of <environmental-var> will be modified and stored in the LINUX environment variable SCIFI_CALIB_PHASE.

Conventions for data taking

At the time that the scan is taken, a number of meta-data has to be recorded:

  • Save run-time information (on local log file and in CALIB_RUN_TABLE of the SciFi Online Database)
    • Run #
    • Run Type
    • Names of relevant recipes (DAQFEE, DAQTELL40, etc.)
    • SiPM temperature and voltage
    • PACIFIC Configuration (should be contained in the Recipe Creation Table of the SciFi Online Database, but some redundancy is ok)
      • gain
      • threshold type
      • Shaper parameter settings
  • Save scan configuration
    • in /calib/sf/ScanConfig/<Run#-RunType-Date&Time>/scanrun.xml
  • Save DAQFEE FSM (excluded device units)
    • also in /calib/sf/ScanConfig/<Run#-RunType-Date&Time>/scanrun.xml
  • Save DAQFEE Tell40 FSM (excluded device units)
    • at present in /group/sf/etc/sfTell40/reports/SF<A,C>/SFCAVERN_<A,C>__<run#>_All_excluded_links.csv
    • should be in /calib/sf/DAQTELL40FSMConfig/<Run#-RunType-Date&Time>/fsmconfig.xml

Conventions for data analysis

At the time the scan data are analyzed, a combination of data and meta-data must be recorded:

  • Save the data themselves
    • normally data are automatically saved to the LHCb Run Database and no extra saving action is then needed
    • however, certain run types do not record standard data banks but special SciFi-specific data (e.g. BER counts), which should then be saved in agreed-upon locations
      • save data in /calib/sf/<Run-Type>/<Run-#>
  • Keep (copies of) all other meta-data in the main analysis working area /calib/sf/${SCIFI_CALIB_PHASE}/<Run-Type>/<Run-#>
    • note that a single calibration can consists of several runs; for each Run-#, create a sub-directory
      • /calib/sf/${SCIFI_CALIB_PHASE}/<Run-Type>/<Run-#>
  • All meta-data that the analysis needs to be self-sufficient should be copied over onto the main analysis areas:
    • DAQFEE Scan & FSM configurations /calib/sf/ScanConfig/<Run#-Run-Type-Date&Time>/scanrun.xml
    • DAQTELL40 configuration /calib/sf/DAQTELL40FSMConfig/<Run#-RunType-Date&Time>/fsmconfig.xml
    • Analysis setup file /group/sf/etc/OnlineDB/ScanAnalysisSetup/<Run-Type>.xml
    • A copy of the database info used to performed the analysis should also be kept (DB's do not keep history of changes)
      • As an example, the FEE Time Calibration Analysis keeps csv or xml TELL40 maps, FEE maps, ... in
        • /calib/sf/${SCIFI_CALIB_PHASE}/<Run-Type>/<Run-#>/input
  • Save analysis results in agreed-upon areas
    • /calib/sf/${SCIFI_CALIB_PHASE}/<Run-Type>/<Run-#>/xml
    • /calib/sf/${SCIFI_CALIB_PHASE}/<Run-Type>/<Run-#>/plots
N.B. In case the results of one calibration are based on data from several runs { Run-#1, Run-#2, Run-#3, ... }, then the <Run-#> referred to in the list above will be, by convention, the first run number of the series { Run-#1, Run-#2, Run-#3, ... }.

FEE Time Calibration

By FEE Time Calibration we intend the procedure to find the best settings of various time phases in the SciFi FE electronics. A number of clocks are used in the SciFi FEE; they are described in detail in the Master Board Manual and in the Cluster Board Manual. An overview is given in the figure below.

pdf.pdf

Figure 3. FEE Clock Scheme

Work on the FEE time calibration has been pioneered during the FEE commissioning, an excellent description of which can be found in Daniel Berninghoff Ph.D. dissertation.

The procedure to scan the phase space of the various clocks to obtain their best calibration is described in detail in section 7 of the Master Board Manual. A internal LHCb note on the analysis of FEE time scan data is currently in preparation (link to be added by Emmy/Lex).

A sub-group of run-types is used to scan the phase space of the FEE time parameters, namely:

  • Time Calibration Scans
    • FPGA_PRBS_BER_TI_SCAN;
    • PACIFIC_BER_TI_SCAN
    • BEAM_TI_SCAN;

The first two calibrate the FEE internal timing, the third one tunes the FEE timing to that of the beam collisions.

FE-Calibration-Sequence.jpg

Relevant Directories

Several directories of the LHCb online file system contain files required for the working of the time calibration. The meaning of the various files is explained below, here we give only an overview of the relevant directories:

  • /calib/sf/{BEAM_TI_SCAN,FPGA_PRBS_BER_TI_SCAN,PACIFIC_BER_TI_SCAN} Contain the timing scan data (one sub-directory per run-no)
  • /calib/sf/ScanConfig Contain the XML dump of the WinCC configuration used for the scan (one sub-directory per run-no)
  • /group/sf/etc/OnlineDB/ScanAnalysisSetup/{BEAM_TI_SCAN,FPGA_PRBS_BER_TI_SCAN,PACIFIC_BER_TI_SCAN} Contain XML files with instructions for the analysis job.
  • /group/sf/etc/OnlineDB/ScanResults/{BEAM_TI_SCAN,FPGA_PRBS_BER_TI_SCAN,PACIFIC_BER_TI_SCAN} Contain XML files with templates for the analysis results.
  • /calib/sf/CavernCommissioning/{BEAM_TI_SCAN,FPGA_PRBS_BER_TI_SCAN,PACIFIC_BER_TI_SCAN} Contain the scan analysis (one sub-directory per run-no, with sub-directories for results, plots etc.)

FPGA Timing Scan

This scan aims at optimizing the clock-domain crossing between the Cluster-FPGA serializer and the Data GBTX and between the Cluster-FPGA main clock and the Cluster-FPGA I/O clock.
The parameters that are calibrated are the so-called FPGA I/O clock and FPGA main clock, described in detail in the Master Board Manual, and denoted in Figure 2 as Data GBTx DesClk 2 and DesClk 0, respectively.

WinCC Scan Configuration

The scan structure used by the DAQFEE WinCC code can be recognized by the automatically-produced scanrun.xml files stored in /calib/sf/ScanConfig. From the example below, one can recognize in the Option tag that the two parameters being scanned are the so-called fpgaIoClockDelay and fpgaMainClockDelay. In practice, the scan configuration consists of two parts: in the first part, the two clocks are stepped at a fixed distance; in the second part, the Cluster-FPGA I/O clock is kept fixed (at the best value previously found, ideally) and the Cluster-FPGA main clock is stepped.

<ScanRun>
 <RunNumber>1234</RunNumber>
 <Recipe>FPGA_PRBS_BER_TI_SCAN</Recipe>
 <MaxSteps>64</MaxSteps>
 <Steps>64</Steps>
 <Start>2022.06.07 11:37:01</Start>
 <Finished>2022.06.07 11:37:01</Finished>
 <Options>
  <pacificSyncPulseDelay>FALSE</pacificSyncPulseDelay>
  <fpgaDataOutMode>FALSE</fpgaDataOutMode>
  <tfcCommandsCDCphase>FALSE</tfcCommandsCDCphase>
  <pacificSyncPatternFixed>FALSE</pacificSyncPatternFixed>
  <fpgaIoClockDelay>TRUE</fpgaIoClockDelay>
  <pacificSyncPulseCDCphase>FALSE</pacificSyncPulseCDCphase>
  <scanType>fpgaPbrsBer</scanType>
  <masterClockDelay>FALSE</masterClockDelay>
  <fpgaMainClockDelay>TRUE</fpgaMainClockDelay>
  <pacificClockDelay>FALSE</pacificClockDelay>
 </Options>

...

</ScanRun>

Then the settings of each step are listed in the Step tag, as in the example below:

<Step nr="1">
  <masterClockDelay>0</masterClockDelay>
  <tfcCmdsCDCphase>0</tfcCmdsCDCphase>
  <fpgaMainClockDelay>0</fpgaMainClockDelay>
  <fpgaIoClockDelay>64</fpgaIoClockDelay>
  <fpgaDataOutMode>2</fpgaDataOutMode>
  <pacificClockDelay>84</pacificClockDelay>
  <pacificSyncPulseDelay>380</pacificSyncPulseDelay>
  <pacificSyncPulseCDCphase>0</pacificSyncPulseCDCphase>
  <pacificSynPatternMode>0</pacificSynPatternMode>
  <pacificSynPattternFixed>0</pacificSynPattternFixed>
 </Step>

Scan Data

The test is based on the so-called GBTX PRBS pattern, generated by the Cluster FPGA in units of 7 bits, referred to as PRBS7 words. Given the 112-bits GBT payload, 16 separate bit-error counters are available for every data link. This data is collected with a hack that somebody else should document in a separate sub-section before this.

Data Analysis

The analysis code uses this data as input and tries to find the best value of the FPGA I/O clock and FPGA main clock, i.e. those for which the number of bit errors is lowest. The goal of the analysis software is described in the /group/sf/etc/OnlineDB/ScanAnalysisSetup/FPGA_PRBS_BER_TI_SCAN.xml file, a preliminary implementation of which is given below:

<ScanAnalysisSetup>
<RunType>FPGA_PRBS_BER_TI_SCAN</RunType>

<ScanResults>
        <BoardType>EMB</BoardType>
        <Table>TIME_CALIB_MB_DATAGBT</Table>
        <CommonGBTDataValue>true</CommonGBTDataValue>
        <GBTData><GBT_N>0</GBT_N><ScanResult desc="FPGA Main" ScanName="fpgaMainClockDelay">CLKDEL0</ScanResult></GBTData>
        <GBTData><GBT_N>0</GBT_N><ScanResult desc="FPGA I/O" ScanName="fpgaIoClockDelay">CLKDEL2</ScanResult></GBTData>
        <GBTData><GBT_N>1</GBT_N><ScanResult desc="FPGA Main" ScanName="fpgaMainClockDelay">CLKDEL0</ScanResult></GBTData>
        <GBTData><GBT_N>1</GBT_N><ScanResult desc="FPGA I/O" ScanName="fpgaIoClockDelay">CLKDEL2</ScanResult></GBTData>
        <GBTData><GBT_N>2</GBT_N><ScanResult desc="FPGA Main" ScanName="fpgaMainClockDelay">CLKDEL0</ScanResult></GBTData>
        <GBTData><GBT_N>2</GBT_N><ScanResult desc="FPGA I/O" ScanName="fpgaIoClockDelay">CLKDEL2</ScanResult></GBTData>
        <GBTData><GBT_N>3</GBT_N><ScanResult desc="FPGA Main" ScanName="fpgaMainClockDelay">CLKDEL0</ScanResult></GBTData>
        <GBTData><GBT_N>3</GBT_N><ScanResult desc="FPGA I/O" ScanName="fpgaIoClockDelay">CLKDEL2</ScanResult></GBTData>
        <GBTData><GBT_N>4</GBT_N><ScanResult desc="FPGA Main" ScanName="fpgaMainClockDelay">CLKDEL0</ScanResult></GBTData>
        <GBTData><GBT_N>4</GBT_N><ScanResult desc="FPGA I/O" ScanName="fpgaIoClockDelay">CLKDEL2</ScanResult></GBTData>
        <GBTData><GBT_N>5</GBT_N><ScanResult desc="FPGA Main" ScanName="fpgaMainClockDelay">CLKDEL0</ScanResult></GBTData>
        <GBTData><GBT_N>5</GBT_N><ScanResult desc="FPGA I/O" ScanName="fpgaIoClockDelay">CLKDEL2</ScanResult></GBTData>
        <GBTData><GBT_N>6</GBT_N><ScanResult desc="FPGA Main" ScanName="fpgaMainClockDelay">CLKDEL0</ScanResult></GBTData>
        <GBTData><GBT_N>6</GBT_N><ScanResult desc="FPGA I/O" ScanName="fpgaIoClockDelay">CLKDEL2</ScanResult></GBTData>
        <GBTData><GBT_N>7</GBT_N><ScanResult desc="FPGA Main" ScanName="fpgaMainClockDelay">CLKDEL0</ScanResult></GBTData>
        <GBTData><GBT_N>7</GBT_N><ScanResult desc="FPGA I/O" ScanName="fpgaIoClockDelay">CLKDEL2</ScanResult></GBTData>
</ScanResults>

</ScanAnalysisSetup>

Calibration Results

The analysis results are stored in XML files; the structure of these XML files can be seen from the template file /group/sf/etc/OnlineDB/ScanResults/FPGA_PRBS_BER_TI_SCAN.xml:

<TimeCalibrationTables>
<RunType>FPGA_PRBS_BER_TI_SCAN</RunType>
<RunNo>
      <NRuns>...</NRuns>
      <array name="list_of_run_no">
      <item>...</item>
      <item>...</item>
          ...
      </array>
</RunNo>

<Entry>
        <Table>TIME_CALIB_MB_DATAGBT</Table>
        <ProdDBId>EMBXXXXX</ProdDBId>
        <ScanResults>
                <GBTData>
                        <GBT_N>0</GBT_N>
                        <CLKDEL0 desc="FPGA Main" ScanName="fpgaMainClockDelay">...</CLKDEL0>
                        <CLKDEL2 desc="FPGA I/O" ScanName="fpgaIoClockDelay">...</CLKDEL2>
                </GBTData>
                <GBTData>
                        <GBT_N>1</GBT_N>
                        <CLKDEL0 desc="FPGA Main" ScanName="fpgaMainClockDelay">...</CLKDEL0>
                        <CLKDEL2 desc="FPGA I/O" ScanName="fpgaIoClockDelay">...</CLKDEL2>
                </GBTData>
                <GBTData>
                        <GBT_N>2</GBT_N>
                        <CLKDEL0 desc="FPGA Main" ScanName="fpgaMainClockDelay">...</CLKDEL0>
                        <CLKDEL2 desc="FPGA I/O" ScanName="fpgaIoClockDelay">...</CLKDEL2>
                </GBTData>
                <GBTData>
                        <GBT_N>3</GBT_N>
                        <CLKDEL0 desc="FPGA Main" ScanName="fpgaMainClockDelay">...</CLKDEL0>
                        <CLKDEL2 desc="FPGA I/O" ScanName="fpgaIoClockDelay">...</CLKDEL2>
                </GBTData>
                <GBTData>
                        <GBT_N>4</GBT_N>
                        <CLKDEL0 desc="FPGA Main" ScanName="fpgaMainClockDelay">...</CLKDEL0>
                        <CLKDEL2 desc="FPGA I/O" ScanName="fpgaIoClockDelay">...</CLKDEL2>
                </GBTData>
                <GBTData>
                        <GBT_N>5</GBT_N>
                        <CLKDEL0 desc="FPGA Main" ScanName="fpgaMainClockDelay">...</CLKDEL0>
                        <CLKDEL2 desc="FPGA I/O" ScanName="fpgaIoClockDelay">...</CLKDEL2>
                </GBTData>
                <GBTData>
                        <GBT_N>6</GBT_N>
                        <CLKDEL0 desc="FPGA Main" ScanName="fpgaMainClockDelay">...</CLKDEL0>
                        <CLKDEL2 desc="FPGA I/O" ScanName="fpgaIoClockDelay">...</CLKDEL2>
                </GBTData>
                <GBTData>
                        <GBT_N>7</GBT_N>
                        <CLKDEL0 desc="FPGA Main" ScanName="fpgaMainClockDelay">...</CLKDEL0>
                        <CLKDEL2 desc="FPGA I/O" ScanName="fpgaIoClockDelay">...</CLKDEL2>
                </GBTData>
        </ScanResults>
</Entry>

</TimeCalibrationTables>

Calibration Plots

Section to be written by Emmy and Lex.

PACIFIC Timing Scan

This scan aims at optimizing the clock-domain crossing between the Cluster-FPGA and PACIFIC ASIC. The parameters that are calibrated are the PACIFIC 320 MHz clock (denoted in Figure 2 as Data GBTx DesClk 3 and DesClk 4), the PACIFIC SyncPulse clock (denoted in Figure 2 as Data GBTx DesClk 7) and the PACIFIC Sync-Pulse Cross-Domain Clock (CDC) phase, described in detail in the Master Board Manual and in the Cluster Board Manual.

WinCC Scan Configuration

The scan structure used by the DAQFEE WinCC code can be recognized by the automatically-produced scanrun.xml files stored in /calib/sf/ScanConfig. From the example below, one can recognize in the Option tag that the three parameters being calibrated are the so-called pacificClockDelay, pacificSyncPulseDelay and pacificSyncPulseCDCphase. Due to our bandwidth limitations, only one quarter of all PACIFIC output lines can be probed at once, and therefore each (pacificClockDelay,pacificSyncPulseDelay,pacificSyncPulseCDCphase) step is repeated four times, each time with a different value of the fpgaDataOutMode selector (8|9|10|11),
During the scan, fpgaIoClockDelay and fpgaMainClockDelay are kept fixed, ideally at the best values determined in the FPGA_PRBS_BER_TI_SCAN scan.
In practice, the scan configuration consists of two parts: in the first part, pacificClockDelay and pacificSyncPulseDelay are stepped at a fixed distance; in the second part, the pacificSyncPulseDelay is kept fixed (at the best value previously found, ideally) and the pacificClockDelay main clock is stepped. The whole procedure is repeated for pacificSyncPulseCDCphase = {0,1}.

<ScanRun>
 <RunNumber>2345</RunNumber>
 <Recipe>PACIFIC_BER_TI_SCAN</Recipe>
 <MaxSteps>40</MaxSteps>
 <Steps>40</Steps>
 <Start>2022.07.13 13:00:49</Start>
 <Finished>1970.01.01 01:00:00</Finished>
 <Options>
  <pacificSyncPulseDelay>TRUE</pacificSyncPulseDelay>
  <fpgaDataOutMode>TRUE</fpgaDataOutMode>
  <tfcCommandsCDCphase>FALSE</tfcCommandsCDCphase>
  <pacificSyncPatternFixed>TRUE</pacificSyncPatternFixed>
  <fpgaIoClockDelay>TRUE</fpgaIoClockDelay>
  <pacificSyncPulseCDCphase>TRUE</pacificSyncPulseCDCphase>
  <scanType>pacificBer</scanType>
  <masterClockDelay>FALSE</masterClockDelay>
  <fpgaMainClockDelay>TRUE</fpgaMainClockDelay>
  <pacificClockDelay>TRUE</pacificClockDelay>
 </Options>
...
</ScanRun>

The settings of each step are listed in the Step tag, as in the example below:

<Step nr="1">
  <masterClockDelay>0</masterClockDelay>
  <tfcCmdsCDCphase>0</tfcCmdsCDCphase>
  <fpgaMainClockDelay>64</fpgaMainClockDelay>
  <fpgaIoClockDelay>128</fpgaIoClockDelay>
  <fpgaDataOutMode>8</fpgaDataOutMode>
  <pacificClockDelay>0</pacificClockDelay>
  <pacificSyncPulseDelay>296</pacificSyncPulseDelay>
  <pacificSyncPulseCDCphase>0</pacificSyncPulseCDCphase>
  <pacificSynPatternMode>1</pacificSynPatternMode>
  <pacificSynPattternFixed>0</pacificSynPattternFixed>
 </Step>

Scan Data

The test is based on the so-called PACIFIC Sync-Pattern, generated by the PACIFIC ASIC. For each PACIFIC output line a separate 8-bit counter (4-bit input concatenated with themselves in reverse order) is generated (technically speaking, the 4-bits pattern is generated by the Cluster FPGA and transferred to 4 single-ended PACIFIC sync-pattern inputs). A custom TELL40 firmware has been developed to analyze the PACIFIC Sync-Pattern and count the number of errors.
This data is collected with a hack that somebody else should document in a separate sub-section before this.

Data Analysis

The analysis code uses this data as input and tries to find the best value of the clock settings, i.e. those for which the number of bit errors is lowest. The goal of the analysis software is described in the /group/sf/etc/OnlineDB/ScanAnalysisSetup/PACIFIC_BER_TI_SCAN.xml file, a preliminary implementation of which is given below:

<ScanAnalysisSetup>
<RunType>PACIFIC_BER_TI_SCAN</RunType>

<ScanResults>
        <BoardType>EMB</BoardType>
        <Table>TIME_CALIB_MB_DATAGBT</Table>
        <CommonGBTDataValue>true</CommonGBTDataValue>
        <GBTData><GBT_N>0</GBT_N><ScanResult desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">CLKDEL3</ScanResult></GBTData>
        <GBTData><GBT_N>0</GBT_N><ScanResult desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">CLKDEL4</ScanResult></GBTData>
        <GBTData><GBT_N>0</GBT_N><ScanResult desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">CLKDEL7</ScanResult></GBTData>
        <GBTData><GBT_N>1</GBT_N><ScanResult desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">CLKDEL3</ScanResult></GBTData>
        <GBTData><GBT_N>1</GBT_N><ScanResult desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">CLKDEL4</ScanResult></GBTData>
        <GBTData><GBT_N>1</GBT_N><ScanResult desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">CLKDEL7</ScanResult></GBTData>
        <GBTData><GBT_N>2</GBT_N><ScanResult desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">CLKDEL3</ScanResult></GBTData>
        <GBTData><GBT_N>2</GBT_N><ScanResult desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">CLKDEL4</ScanResult></GBTData>
        <GBTData><GBT_N>2</GBT_N><ScanResult desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">CLKDEL7</ScanResult></GBTData>
        <GBTData><GBT_N>3</GBT_N><ScanResult desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">CLKDEL3</ScanResult></GBTData>
        <GBTData><GBT_N>3</GBT_N><ScanResult desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">CLKDEL4</ScanResult></GBTData>
        <GBTData><GBT_N>3</GBT_N><ScanResult desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">CLKDEL7</ScanResult></GBTData>
        <GBTData><GBT_N>4</GBT_N><ScanResult desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">CLKDEL3</ScanResult></GBTData>
        <GBTData><GBT_N>4</GBT_N><ScanResult desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">CLKDEL4</ScanResult></GBTData>
        <GBTData><GBT_N>4</GBT_N><ScanResult desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">CLKDEL7</ScanResult></GBTData>
        <GBTData><GBT_N>5</GBT_N><ScanResult desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">CLKDEL3</ScanResult></GBTData>
        <GBTData><GBT_N>5</GBT_N><ScanResult desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">CLKDEL4</ScanResult></GBTData>
        <GBTData><GBT_N>5</GBT_N><ScanResult desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">CLKDEL7</ScanResult></GBTData>
        <GBTData><GBT_N>6</GBT_N><ScanResult desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">CLKDEL3</ScanResult></GBTData>
        <GBTData><GBT_N>6</GBT_N><ScanResult desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">CLKDEL4</ScanResult></GBTData>
        <GBTData><GBT_N>6</GBT_N><ScanResult desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">CLKDEL7</ScanResult></GBTData>
        <GBTData><GBT_N>7</GBT_N><ScanResult desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">CLKDEL3</ScanResult></GBTData>
        <GBTData><GBT_N>7</GBT_N><ScanResult desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">CLKDEL4</ScanResult></GBTData>
        <GBTData><GBT_N>7</GBT_N><ScanResult desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">CLKDEL7</ScanResult></GBTData>
</ScanResults>

<ScanResults>
        <BoardType>ECB</BoardType>
        <Table>TIME_CALIB_CB</Table>
        <ScanResult desc="Pacific Sync Pulse CDC phase" ScanName="pacificSyncPulseCDCphase">FPGA0_SYNC_PULSE_PHASE</ScanResult>
        <ScanResult desc="Pacific Sync Pulse CDC phase" ScanName="pacificSyncPulseCDCphase">FPGA1_SYNC_PULSE_PHASE</ScanResult>
        <ScanResult desc="Select channel group" ScanName="fpgaDataOutMode">FPGA0_DATAOUT_MODE</ScanResult>
        <ScanResult desc="Select channel group" ScanName="fpgaDataOutMode">FPGA1_DATAOUT_MODE</ScanResult>
        <ScanResult desc="PACIFIC Test-Pattern mode" ScanName="pacificSynPatternMode">FPGA0_SYNC_PATTERN_PCFC</ScanResult>
        <ScanResult desc="PACIFIC Test-Pattern mode" ScanName="pacificSynPatternMode">FPGA1_SYNC_PATTERN_PCFC</ScanResult>
        <ScanResult desc="Fixed PACIFIC Test-Pattern" ScanName="pacificSynPatternFixed">FPGA0_SYNC_PATTERN_FIXED</ScanResult>
        <ScanResult desc="Fixed PACIFIC Test-Pattern" ScanName="pacificSynPatternFixed">FPGA1_SYNC_PATTERN_FIXED</ScanResult>
</ScanResults>

</ScanAnalysisSetup>

Calibration Results

The analysis results are stored in XML files; the structure of these XML files can be seen from the template file /group/sf/etc/OnlineDB/ScanResults/PACIFIC_BER_TI_SCAN.xml:

<TimeCalibrationTables>
<RunType>PACIFIC_BER_TI_SCAN</RunType>
<RunNo>
      <NRuns>...</NRuns>
      <array name="list_of_run_no">
      <item>...</item>
      <item>...</item>
          ...
      </array>
</RunNo>

<Entry>
        <Table>TIME_CALIB_MB_DATAGBT</Table>
        <ProdDBId>EMBXXXXX</ProdDBId>
        <ScanResults>
                <GBTData>
                        <GBT_N>0</GBT_N>
                        <CLKDEL3 desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">...</CLKDEL3>
                        <CLKDEL4 desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">...</CLKDEL4>
                        <CLKDEL7 desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">...</CLKDEL7>
                </GBTData>
                <GBTData>
                        <GBT_N>1</GBT_N>
                        <CLKDEL3 desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">...</CLKDEL3>
                        <CLKDEL4 desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">...</CLKDEL4>
                        <CLKDEL7 desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">...</CLKDEL7>
                </GBTData>
                <GBTData>
                        <GBT_N>2</GBT_N>
                        <CLKDEL3 desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">...</CLKDEL3>
                        <CLKDEL4 desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">...</CLKDEL4>
                        <CLKDEL7 desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">...</CLKDEL7>
                </GBTData>
                <GBTData>
                        <GBT_N>3</GBT_N>
                        <CLKDEL3 desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">...</CLKDEL3>
                        <CLKDEL4 desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">...</CLKDEL4>
                        <CLKDEL7 desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">...</CLKDEL7>
                </GBTData>
                <GBTData>
                        <GBT_N>4</GBT_N>
                        <CLKDEL3 desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">...</CLKDEL3>
                        <CLKDEL4 desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">...</CLKDEL4>
                        <CLKDEL7 desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">...</CLKDEL7>
                </GBTData>
                <GBTData>
                        <GBT_N>5</GBT_N>
                        <CLKDEL3 desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">...</CLKDEL3>
                        <CLKDEL4 desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">...</CLKDEL4>
                        <CLKDEL7 desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">...</CLKDEL7>
                </GBTData>
                <GBTData>
                        <GBT_N>6</GBT_N>
                        <CLKDEL3 desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">...</CLKDEL3>
                        <CLKDEL4 desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">...</CLKDEL4>
                        <CLKDEL7 desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">...</CLKDEL7>
                </GBTData>
                <GBTData>
                        <GBT_N>7</GBT_N>
                        <CLKDEL3 desc="PACIFIC Clk 0/2" ScanName="pacificClockDelay">...</CLKDEL3>
                        <CLKDEL4 desc="PACIFIC Clk 1/3" ScanName="pacificClockDelay">...</CLKDEL4>
                        <CLKDEL7 desc="PACIFIC Sync" ScanName="pacificSyncPulseDelay">...</CLKDEL7>
                </GBTData>
        </ScanResults>
</Entry>

<Entry>
        <Table>TIME_CALIB_CB</Table>
        <ProdDBId>ECBXXXXX</ProdDBId>
        <ScanResults>
                <FPGA0_SYNC_PULSE_PHASE desc="Pacific Sync Pulse CDC phase" ScanName="pacificSyncPulseCDCphase">...</PACIFIC_SYNCP_CDC_PHASE>
                <FPGA1_SYNC_PULSE_PHASE desc="Pacific Sync Pulse CDC phase" ScanName="pacificSyncPulseCDCphase">...</PACIFIC_SYNCP_CDC_PHASE>
                <FPGA0_DATAOUT_MODE desc="Select channel group" ScanName="fpgaDataOutMode">...</FPGA0_DATAOUT_MODE>
                <FPGA1_DATAOUT_MODE desc="Select channel group" ScanName="fpgaDataOutMode">...</FPGA1_DATAOUT_MODE>
                <FPGA0_SYNC_PATTERN_PCFC desc="PACIFIC Test-Pattern mode" ScanName="pacificSynPatternMode">...</FPGA0_SYNC_PATTERN_PCFC>
                <FPGA1_SYNC_PATTERN_PCFC desc="PACIFIC Test-Pattern mode" ScanName="pacificSynPatternMode">...</FPGA1_SYNC_PATTERN_PCFC>
                <FPGA0_SYNC_PATTERN_FIXED desc="Fixed PACIFIC Test-Pattern" ScanName="pacificSynPatternFixed">...</FPGA0_SYNC_PATTERN_FIXED>
                <FPGA1_SYNC_PATTERN_FIXED desc="Fixed PACIFIC Test-Pattern" ScanName="pacificSynPatternFixed">...</FPGA1_SYNC_PATTERN_FIXED>
        </ScanResults>
</Entry>

</TimeCalibrationTables>

Calibration Plots

Section to be written by Emmy and Lex.

Beam Timing Scan

This scan aims at optimizing the SciFi FEE time phase with respect to beam interactions. A pre-requisite for carrying out this scan is that the BX value associated to the data is the same for all the FEE; this is in practice defined by the phase of the TFC commands (most notably BX Reset), which needs then to be adjusted. The SciFi FEE has provisions to adjust the phase of the TFC commands, namely TFC Delay line in Figure 2. This parameter could be scanned per data link; however, it is preferred and recommended to adjust this delay per control link using the timing offset in the SOL40.

Once the BX adjustment (sometime referred to as coarse time calibration) has been performed, the parameter that is calibrated is the Master GBT clock phase (denoted in Figure 2 as 40 MHz Ref clock), described in detail in the Master Board Manual. Eight Master-GBTx deskewable clock outputs are reference clocks to eight Data-GBTx. Moreover, since the TFC commands cross clock domain (from TFC clock to FPGA main clock), a phase-selection bit has been foreseen in the FEE (denoted in Figure 2 as TFC 40 MHz CDC) that permits to avoid setup-and-hold time violations (see Section 7.3 of the Master Board Manual).

Wilco's remark to be handled: thinking about this, the pacificSyncPulseCDCphase should be included.
When shifting the the MasterGBT clock, you will shift the reference from the Pacific sync pulse clock(DataGBT), w.r.t. to the TFC 
clock(MstrGBT). This signal is not fine time important because the Pacific sync pulse is not BciD event related,
but if the sampling of the FE_rst is missed due to sampling on the edge, the Pacifics don't receive their sync pulse.
Probably this will be difficult to detect during a scan. It needs some thinking.

WinCC Scan Configuration

The scan structure used by the DAQFEE WinCC code can be recognized by the automatically-produced scanrun.xml files stored in /calib/sf/ScanConfig. From the example below, one can recognize in the Option tag that the two parameters being calibrated are the so-called masterClockDelay and tfcCommandsCDCphase. During the scan, fpgaIoClockDelay, fpgaMainClockDelay, pacificClockDelay, pacificSyncPulseDelay and pacificSyncPulseCDCphase are kept fixed, ideally at the best values determined in the FPGA_PRBS_BER_TI_SCAN and PACIFIC_BER_TI_SCAN scan.

<ScanRun>
 <RunNumber>1234</RunNumber>
 <Recipe>BEAM_TI_SCAN</Recipe>
 <MaxSteps>64</MaxSteps>
 <Steps>64</Steps>
 <Start>2022.08.02 15:12:46</Start>
 <Finished>1970.01.01 01:00:00</Finished>
 <Options>
  <pacificSyncPulseDelay>FALSE</pacificSyncPulseDelay>
  <fpgaDataOutMode>FALSE</fpgaDataOutMode>
  <tfcCommandsCDCphase>TRUE</tfcCommandsCDCphase>
  <pacificSyncPatternFixed>FALSE</pacificSyncPatternFixed>
  <fpgaIoClockDelay>FALSE</fpgaIoClockDelay>
  <pacificSyncPulseCDCphase>FALSE</pacificSyncPulseCDCphase>
  <scanType>beam</scanType>
  <masterClockDelay>TRUE</masterClockDelay>
  <fpgaMainClockDelay>FALSE</fpgaMainClockDelay>
  <pacificClockDelay>FALSE</pacificClockDelay>
 </Options>

...

</ScanRun>

The settings of each step are listed in the Step tag, as in the example below:

<Step nr="1">
  <masterClockDelay>0</masterClockDelay>
  <tfcCmdsCDCphase>0</tfcCmdsCDCphase>
  <fpgaMainClockDelay>64</fpgaMainClockDelay>
  <fpgaIoClockDelay>128</fpgaIoClockDelay>
  <fpgaDataOutMode>0</fpgaDataOutMode>
  <pacificClockDelay>84</pacificClockDelay>
  <pacificSyncPulseDelay>380</pacificSyncPulseDelay>
  <pacificSyncPulseCDCphase>0</pacificSyncPulseCDCphase>
  <pacificSynPatternMode>0</pacificSynPatternMode>
  <pacificSynPattternFixed>0</pacificSynPattternFixed>
 </Step>

Scan Data

Cluster Data? To be written by experts like Snow.

Data Analysis

The analysis code uses this data as input and tries to find the best value of the clock settings, i.e. those for which the number of bit errors is lowest. The goal of the analysis software is described in the /group/sf/etc/OnlineDB/ScanAnalysisSetup/BEAM_TI_SCAN.xml file, a preliminary implementation of which is given below:

<ScanAnalysisSetup>
<RunType>BEAM_TI_SCAN</RunType>

<ScanResults>
        <BoardType>EMB</BoardType>
        <Table>TIME_CALIB_MB</Table>
        <ScanResult desc="" ScanName="masterClockDelay">MASTER_CLKDEL0</ScanResult>
        <ScanResult desc="" ScanName="masterClockDelay">MASTER_CLKDEL1</ScanResult>
        <ScanResult desc="" ScanName="masterClockDelay">MASTER_CLKDEL2</ScanResult>
        <ScanResult desc="" ScanName="masterClockDelay">MASTER_CLKDEL3</ScanResult>
        <ScanResult desc="" ScanName="masterClockDelay">MASTER_CLKDEL4</ScanResult>
        <ScanResult desc="" ScanName="masterClockDelay">MASTER_CLKDEL5</ScanResult>
        <ScanResult desc="" ScanName="masterClockDelay">MASTER_CLKDEL6</ScanResult>
        <ScanResult desc="" ScanName="masterClockDelay">MASTER_CLKDEL7</ScanResult>
</ScanResults>

<ScanResults>
        <BoardType>ECB</BoardType>
        <Table>TIME_CALIB_CB</Table>
        <ScanResult desc="TFC to main clock CDC phase" ScanName="tfcCommandsCDCphase">FPGA0_TFC_COM_PHASE</ScanResult>
        <ScanResult desc="TFC to main clock CDC phase" ScanName="tfcCommandsCDCphase">FPGA1_TFC_COM_PHASE</ScanResult>
</ScanResults>

</ScanAnalysisSetup>

Calibration Results

The analysis results are stored in XML files; the structure of these XML files can be seen from the template file /group/sf/etc/OnlineDB/ScanResults/BEAM_TI_SCAN.xml:

<TimeCalibrationTables>
<RunType>BEAM_TI_SCAN</RunType>
<RunNo>
      <NRuns>...</NRuns>
      <array name="list_of_run_no">
      <item>...</item>
      <item>...</item>
          ...
      </array>
</RunNo>

<Entry>
        <Table>TIME_CALIB_MB</Table>
        <ProdDBId>EMBXXXXX</ProdDBId>
        <ScanResults>
                <MASTER_CLKDEL0 desc="" ScanName="masterClockDelay">...</MASTER_CLKDEL0>
                <MASTER_CLKDEL1 desc="" ScanName="masterClockDelay">...</MASTER_CLKDEL1>
                <MASTER_CLKDEL2 desc="" ScanName="masterClockDelay">...</MASTER_CLKDEL2>
                <MASTER_CLKDEL3 desc="" ScanName="masterClockDelay">...</MASTER_CLKDEL3>
                <MASTER_CLKDEL4 desc="" ScanName="masterClockDelay">...</MASTER_CLKDEL4>
                <MASTER_CLKDEL5 desc="" ScanName="masterClockDelay">...</MASTER_CLKDEL5>
                <MASTER_CLKDEL6 desc="" ScanName="masterClockDelay">...</MASTER_CLKDEL6>
                <MASTER_CLKDEL7 desc="" ScanName="masterClockDelay">...</MASTER_CLKDEL7>
        </ScanResults>
</Entry>

<Entry>
        <Table>TIME_CALIB_CB</Table>
        <ProdDBId>ECBXXXXX</ProdDBId>
        <ScanResults>
                <FPGA0_TFC_COM_PHASE desc="TFC to main clock CDC phase" ScanName="tfcCommandsCDCphase">...</FPGA0_TFC_COM_PHASE>
                <FPGA1_TFC_COM_PHASE desc="TFC to main clock CDC phase" ScanName="tfcCommandsCDCphase">...</FPGA1_TFC_COM_PHASE>
        </ScanResults>
</Entry>

</TimeCalibrationTables>

Calibration Plots

Section to be written by Snow and Marc.

Optical Link Calibration

On each FE Box, 8 VTTx dual transmitter convert the serial data of the 16 GBTx serializers to 4.8 Gbits/s 850 nm optical streams. The optical output of the VTTx can be tuned by adjusting the bias and modulation currents of the so-called GBLD ASIC. By Optical Link Calibration we intend the procedure to find the best settings of the VTTx bias current.

WinCC Scan Configuration

The scan structure used by the DAQFEE WinCC code can be recognized by the automatically-produced scanrun.xml files stored in /calib/sf/ScanConfig. From the example below, one can recognize in the Option tag that the parameter being scanned is the so-called iBias.

not yet found

The settings of each step are listed in the Step tag, as in the example below:

not yet found

Scan Data

The test is based on the so-called GBTX PRBS pattern, generated by the Cluster FPGA in units of 7 bits, referred to as PRBS7 words. Given the 112-bits GBT payload, 16 separate bit-error counters are available for every data link. This data is collected with a hack that somebody else should document in a separate sub-section before this.

Data Analysis

The analysis code uses this data as input and tries to find the best value of the VTTx bias current, i.e. that for which the number of bit errors is lowest. The goal of the analysis software is described in the /group/sf/etc/OnlineDB/ScanAnalysisSetup/VTTXBIAS_SCAN.xml file, a preliminary implementation of which is given below:

<ScanAnalysisSetup>
<RunType>VTTXBIAS_SCAN</RunType>

<ScanResults>
        <BoardType>EMB</BoardType>
        <Table>TIME_CALIB_MB_DATAGBT</Table>
        <CommonGBTDataValue>true</CommonGBTDataValue>
        <GBTData><GBT_N>0</GBT_N><ScanResult desc="" ScanName="iBias">VTTX_IBIAS</ScanResult></GBTData>
        <GBTData><GBT_N>1</GBT_N><ScanResult desc="" ScanName="iBias">VTTX_IBIAS</ScanResult></GBTData>
        <GBTData><GBT_N>2</GBT_N><ScanResult desc="" ScanName="iBias">VTTX_IBIAS</ScanResult></GBTData>
        <GBTData><GBT_N>3</GBT_N><ScanResult desc="" ScanName="iBias">VTTX_IBIAS</ScanResult></GBTData>
        <GBTData><GBT_N>4</GBT_N><ScanResult desc="" ScanName="iBias">VTTX_IBIAS</ScanResult></GBTData>
        <GBTData><GBT_N>5</GBT_N><ScanResult desc="" ScanName="iBias">VTTX_IBIAS</ScanResult></GBTData>
        <GBTData><GBT_N>6</GBT_N><ScanResult desc="" ScanName="iBias">VTTX_IBIAS</ScanResult></GBTData>
        <GBTData><GBT_N>7</GBT_N><ScanResult desc="" ScanName="iBias">VTTX_IBIAS</ScanResult></GBTData>
        </ScanResults>
</ScanResults>

</ScanAnalysisSetup>
Calibration Results

The analysis results are stored in XML files; the structure of these XML files can be seen from the template file /group/sf/etc/OnlineDB/ScanResults/VTTXBIAS_SCAN.xml:

<TimeCalibrationTables>
<RunType>VTTXBIAS_SCAN</RunType>
<RunNo>
      <NRuns>...</NRuns>
      <array name="list_of_run_no">
      <item>...</item>
      <item>...</item>
          ...
      </array>
</RunNo>

<Entry>
        <Table>TIME_CALIB_MB_DATAGBT</Table>
        <ProdDBId>EMBXXXXX</ProdDBId>
        <ScanResults>
                <GBTData>
                        <GBT_N>0</GBT_N>
                        <VTTX_IBIAS ScanName="iBias" Desc="">...</VTTX_IBIAS>
                </GBTData>
                <GBTData>
                        <GBT_N>1</GBT_N>
                        <VTTX_IBIAS ScanName="iBias" Desc="">...</VTTX_IBIAS>
                </GBTData>
                <GBTData>
                        <GBT_N>2</GBT_N>
                        <VTTX_IBIAS ScanName="iBias" Desc="">...</VTTX_IBIAS>
                </GBTData>
                <GBTData>
                        <GBT_N>3</GBT_N>
                        <VTTX_IBIAS ScanName="iBias" Desc="">...</VTTX_IBIAS>
                </GBTData>
                <GBTData>
                        <GBT_N>4</GBT_N>
                        <VTTX_IBIAS ScanName="iBias" Desc="">...</VTTX_IBIAS>
                </GBTData>
                <GBTData>
                        <GBT_N>5</GBT_N>
                        <VTTX_IBIAS ScanName="iBias" Desc="">...</VTTX_IBIAS>
                </GBTData>
                <GBTData>
                        <GBT_N>6</GBT_N>
                        <VTTX_IBIAS ScanName="iBias" Desc="">...</VTTX_IBIAS>
                </GBTData>
                <GBTData>
                        <GBT_N>7</GBT_N>
                        <VTTX_IBIAS ScanName="iBias" Desc="">...</VTTX_IBIAS>
                </GBTData>
        </ScanResults>
</Entry>

</TimeCalibrationTables>

Calibration Plots

Section to be written by Wilco.

FEE Threshold Calibration

What is described in this section is currently not implemented but rather a proposal - Lukas

The FEE Threshold Calibration aims at finding the best settings for the PACIFIC comparator thresholds (Vth1, Vth2, Vth3) for physics data taking. The calibration constants are obtained from the analysis of the so-called Light Injection Threshold Scan, in which the light injection system (LIS) is used to inject pulsed light into the fibre mats, close to the SiPMs, while the comparator threshold DACs are scanned. The light injection threshold scans probe the full frontend chain of the SiPMs + FEEs and can thus also help to find faulty SiPM and/or PACIFIC channels.

In the so-called Charge Injection Scan, a known fixed charge is injected directly into the PACIFIC channels while the comparator threshold DACs are scanned. This scan is therefore complementary to the LIS scan, in that it probes only the FEEs.

Work on the FEE threshold calibration has been pioneered during the FEE commissioning, an excellent description of which can be found in Daniel Berninghoff Ph.D. dissertation.

A sub-group of run-types is used to scan the phase space of the LIS parameters and the PACIFIC comparators.
Scan Types:

  • CHARGE_TH_SCAN
  • LIS_TH_SCAN

Relevant Directories

Several directories of the LHCb online file system contain files required for the working of the threshold calibration. The meaning of the various files is explained below, here we give only an overview of the relevant directories:

  • /hlt2/objects/SF/<Run-#> Contain the mdf files
  • /calib/sf/{CHARGE_TH_SCAN,LIS_TH_SCAN}/<Run-#> Contain the decoded scan data for the corresponding run number
  • /calib/sf/ScanConfig Contain the XML dump of the WinCC configuration used for the scan (one sub-directory per run number)
  • /group/sf/etc/OnlineDB/ScanAnalysisSetup/{CHARGE_TH_SCAN,LIS_TH_SCAN}.xml Contain XML files with instructions for the analysis job
  • /group/sf/etc/OnlineDB/ScanResults/{CHARGE_TH_SCAN,LIS_TH_SCAN}.xml Contain XML files with templates for the analysis results
  • /calib/sf/${SCIFI_CALIB_PHASE}/{CHARGE_TH_SCAN,LIS_TH_SCAN}/<Date&Time> Contain the Scurves constructed from the decoded mdf files, as well as any further analysis results and plots

Scan Data

The SciFi data processing module in the TELL40 implements embedded 16‐bit counters that continuously update histograms of the hit caused by NZS commands in each PACIFIC channel. All histograms counters (that can also be read out via ECS) are written out in dedicated COUNTER fragments upon reception of a trigger condition, adjustable by ECS. The typical application is indeed in step-runs, like LIS_TH_SCAN, during which COUNTER fragments are written out at the end of each step. A detailed description of the Counter fragments can be found in the SciFi Tracker TELL40 Data Processing EDMS 1904563.

Light Injection Threshold Scan

This scan aims at scanning the PACIFIC comparator thresholds (Vth1, Vth2, Vth3) while injecting pulsed light into the fibre mats. Fitting so-called Scurves to the resulting SiPM hit spectrum allows the reconstruction of the photon-peak positions, the distance among which in turn provides the DAC-to-photoelectron conversion.

The Light injection pulse is triggered by the TFC Calibration(2) command (called Calib C in the TFC control panels). The pulse phase and width can be set through lisStart and lisStop (the deskewable clocks CLKDES5 and CLKDES6 of Data-GBT Nr. 3), corresponding to a maximum pulse length of 25 ns. A pulse width longer than 25ns can be obtained through the lisPulseExt (LIS_PULSELEN). Because the LIS pulse is triggered by the TFC Calibration(2) command, the LIS pulse clock domain and the TFC clock domain cross each other: therefore the right phase-shift of the Calib(2) command must be selected by lisPulseCDCphase (LIS_INPHASE) to avoid meta-stabilities. This procedure is described in detail in the Master Board Manual.

WinCC Scan Configuration

The scan structure used by the DAQFEE WinCC code can be recognized by the automatically-produced scanrun.xml files stored in /calib/sf/ScanConfig. From the example below, one can recognize in the Option tag that the parameters being calibrated are the three comparator thresholds selectVth{1,23}, and the LIS pulse settings lisPulse, lisPulseExt and lisPulseCDCphase; one can also see that the values set at each step are those of vth1,2,3, lisStart, lisStop, lisPulseExt and lisPulseCDCphase.

<ScanRun>
 <RunNumber>1234</RunNumber>
 <Recipe>LIS_TH_SCAN</Recipe>
 <MaxSteps>768</MaxSteps>
 <Steps>768</Steps>
 <Start>2022.06.15 12:44:08</Start>
 <Finished>1970.01.01 01:00:00</Finished>
 <Options>
  <chargeInjectionDelay>FALSE</chargeInjectionDelay>
  <lisPulseCDCphase>TRUE</lisPulseCDCphase>
  <chargePulseCDCphase>FALSE</chargePulseCDCphase>
  <selectVth3>TRUE</selectVth3>
  <selectVth2>TRUE</selectVth2>
  <selectVth1>TRUE</selectVth1>
  <lisPulse>TRUE</lisPulse>
  <scanType>thLis</scanType>
  <pacificVthsMode>local</pacificVthsMode>
  <lisPulseExt>TRUE</lisPulseExt>
 </Options>

...

</ScanRun>

The settings of each step are listed in the Step tag, as in the example below:

<Step nr="1">
  <vth1>1</vth1>
  <vth2>0</vth2>
  <vth3>0</vth3>
  <lisStart>0</lisStart>
  <lisStop>0</lisStop>
  <lisPulseCDCphase>0</lisPulseCDCphase>
  <lisPulseExt>0</lisPulseExt>
  <chargeInjDelay>0</chargeInjDelay>
  <chargePulseCDCphase>0</chargePulseCDCphase>
 </Step>

Data Analysis

Analysis Goals

The analysis code uses this data as input and tries to find the best value of the LIS settings and to equalize all threshold settings. The goal of the analysis software is described in the /group/sf/etc/OnlineDB/ScanAnalysisSetup/LIS_TH_SCAN.xml file, a preliminary implementation of which is given below:

<ScanAnalysisSetup>
<RunType>LIS_TH_SCAN</RunType>

<ScanResults>
        <BoardType>EMB</BoardType>
        <Table>TH_CALIB_MB</Table>
        <ScanResult desc="LIS pulse extension. +x*25ns" ScanName="lisPulseExt">LIS_PULSELEN</ScanResult>
        <ScanResult desc="LIS pulse CDC phase" ScanName="lisPulseCDCphase">LIS_INPHASE</ScanResult>
</ScanResults>

<ScanResults>
        <BoardType>EMB</BoardType>
        <Table>TH_CALIB_MB_DATAGBT</Table>
        <GBTData><GBT_N>3</GBT_N><ScanResult desc="LIS Pulse Start" ScanName="lisStart">CLKDEL5</ScanResult></GBTData>
        <GBTData><GBT_N>3</GBT_N><ScanResult desc="LIS Pulse Stop" ScanName="lisStop">CLKDEL6</ScanResult></GBTData>
</ScanResults>

<ScanResults>
        <BoardType>EPA</BoardType>
        <Table>TH_CALIB_ASIC</Table>
        <<COMMONVTH>1</<COMMONVTH><ScanResult desc=Fit Chi2>CHI2_LIS</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Fit Gain>GAIN_LIS</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE00>DAC_PE00</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE05>DAC_PE05</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE10>DAC_PE10</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE15>DAC_PE15</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE20>DAC_PE20</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE25>DAC_PE25</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE30>DAC_PE30</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE35>DAC_PE35</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE40>DAC_PE40</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE45>DAC_PE45</ScanResult>
        <COMMONVTH>1</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V1 for PE50>DAC_PE50</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Fit Chi2>CHI2_LIS</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Fit Gain>GAIN_LIS</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE00>DAC_PE00</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE05>DAC_PE05</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE10>DAC_PE10</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE15>DAC_PE15</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE20>DAC_PE20</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE25>DAC_PE25</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE30>DAC_PE30</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE35>DAC_PE35</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE40>DAC_PE40</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE45>DAC_PE45</ScanResult>
        <COMMONVTH>2</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V2 for PE50>DAC_PE50</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Fit Chi2>CHI2_LIS</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Fit Gain>GAIN_LIS</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE00>DAC_PE00</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE05>DAC_PE05</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE10>DAC_PE10</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE15>DAC_PE15</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE20>DAC_PE20</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE25>DAC_PE25</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE30>DAC_PE30</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE35>DAC_PE35</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE40>DAC_PE40</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE45>DAC_PE45</ScanResult>
        <COMMONVTH>3</<COMMONVTH><ScanResult desc=Common PACIFIC Threshold Value V3 for PE50>DAC_PE50</ScanResult>
</ScanResults>

<ScanResults>
        <BoardType>EPA</BoardType>
        <Table>TH_CALIB_ASIC_LCLVTH</Table>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=Fit Chi2>CHI2_LIS</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=Fit Gain>GAIN_LIS</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE00>DAC_PE00</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE05>DAC_PE05</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE10>DAC_PE10</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE15>DAC_PE15</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE20>DAC_PE20</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE25>DAC_PE25</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE30>DAC_PE30</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE35>DAC_PE35</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE40>DAC_PE40</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE45>DAC_PE45</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE50>DAC_PE50</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=Fit Chi2>CHI2_LIS</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=Fit Gain>GAIN_LIS</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE00>DAC_PE00</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE05>DAC_PE05</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE10>DAC_PE10</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE15>DAC_PE15</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE20>DAC_PE20</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE25>DAC_PE25</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE30>DAC_PE30</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE35>DAC_PE35</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE40>DAC_PE40</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE45>DAC_PE45</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE50>DAC_PE50</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=Fit Chi2>CHI2_LIS</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=Fit Gain>GAIN_LIS</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE00>DAC_PE00</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE05>DAC_PE05</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE10>DAC_PE10</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE15>DAC_PE15</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE20>DAC_PE20</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE25>DAC_PE25</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE30>DAC_PE30</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE35>DAC_PE35</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE40>DAC_PE40</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE45>DAC_PE45</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE50>DAC_PE50</ScanResult>

         ...

        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=Fit Chi2>CHI2_LIS</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=Fit Gain>GAIN_LIS</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE00>DAC_PE00</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE05>DAC_PE05</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE10>DAC_PE10</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE15>DAC_PE15</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE20>DAC_PE20</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE25>DAC_PE25</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE30>DAC_PE30</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE35>DAC_PE35</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE40>DAC_PE40</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE45>DAC_PE45</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for PE50>DAC_PE50</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=Fit Chi2>CHI2_LIS</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=Fit Gain>GAIN_LIS</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE00>DAC_PE00</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE05>DAC_PE05</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE10>DAC_PE10</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE15>DAC_PE15</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE20>DAC_PE20</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE25>DAC_PE25</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE30>DAC_PE30</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE35>DAC_PE35</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE40>DAC_PE40</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE45>DAC_PE45</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for PE50>DAC_PE50</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=Fit Chi2>CHI2_LIS</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=Fit Gain>GAIN_LIS</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE00>DAC_PE00</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE05>DAC_PE05</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE10>DAC_PE10</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE15>DAC_PE15</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE20>DAC_PE20</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE25>DAC_PE25</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE30>DAC_PE30</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE35>DAC_PE35</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE40>DAC_PE40</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE45>DAC_PE45</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for PE50>DAC_PE50</ScanResult>
</ScanResults>

</ScanAnalysisSetup>

Raw Bank Decoding

The first analysis step, after taking the data (technically this can also be run during the data taking as part of a special HLT2 sequence), consists of decoding the FTCalibration raw banks to extract the counter values and saving them to root files. The sequence consists of FTCounterDecoder and FTCounterWriter. The decoded counters are saved as root files to /calib/sf/LIS_TH_SCAN/<RUNNUMBER>/<RUNNUMBER>_decoded.root

Scurve Creation

A LIS_TH_SCAN can be comprised of multiple runs. In order to build correct Scurves it is necessary to combine the data from all runs. The Scurves are stored in /calib/sf/<ENV_VAR>/LIS_TH_SCAN/<DATE_TIME>/root/<RUN_NUMBER>_scurves.root. In case the Scurves are constructed from multiple runs <RUN_NUMBER> refers to the first run. Any configuration files needed to convert the FTCounters to Scurves, e.g. the scanrun.xml file, should be copied to /calib/sf/<ENV_VAR>/LIS_TH_SCAN/<DATE_TIME>/<RUN_NUMBER>.

Scurve Fitting & Threshold Calculation

In order to calibrate the PACIFIC comparator thresholds, meaning converting the signal amplitude from digital values (DAC) to photoelectrons (pe), each individual Scurve is fitted. The fit results are stored in /calib/sf/<ENV_VAR>/LIS_TH_SCAN/<DATE_TIME>/root/</RUN_NUMBER>_calibration.root and plots are saved in /calib/sf/<ENV_VAR>/LIS_TH_SCAN/<DATE_TIME>/plots/. The threshold values for each of the three comparators of one channel are calculated from the fit parameters and saved to an xml file in /calib/sf/<ENV_VAR>/LIS_TH_SCAN/<DATE_TIME>/xml/. Since we always take data for both integrators, their results are merged. In the event that the calibration fit yields exceptional results, e.g. gain = 0, the corresponding channel should be flagged and default values should be written to the XML file.

Database Export

If the calibration results are satisfactory they are exported to the calibration database.

Calibration Results

The analysis results are stored in XML files; the structure of these XML files can be seen from the template file /group/sf/etc/OnlineDB/ScanResults/LIS_TH_SCAN.xml:

<ThCalibrationTables>
<RunType>LIS_TH_SCAN</RunType>
<RunNo>
        <NRuns>...</NRuns>
        <array name="list_of_run_no">
                <item>...</item>
                <item>...</item>
                ...
        </array>
</RunNo>

<Entry>
        <Table>TH_CALIB_MB</Table>
        <ProdDBId>EMBXXXXX</ProdDBId>
        <ScanResults>
                <LIS_PULSELEN desc="LIS pulse extension. +x*25ns" ScanName="lisPulseExt">...</LIS_PULSELEN>
                <LIS_INPHASE desc="LIS pulse CDC phase" ScanName="lisPulseCDCphase">...</LIS_INPHASE>
        </ScanResults>
</Entry>

<Entry>
        <Table>TH_CALIB_MB_DATAGBT</Table>
        <ProdDBId>EMBXXXXX</ProdDBId>
        <ScanResults>
                <GBTData>
                        <GBT_N>3</GBT_N>
                        <CLKDEL5 desc="LIS Pulse Start" ScanName="lisStart">...</CLKDEL5>
                        <CLKDEL6 desc="LIS Pulse Stop" ScanName="lisStop">...</CLKDEL6>
                </GBTData>
        </ScanResults>
</Entry>

<Entry>
        <Table>TH_CALIB_ASIC</Table>
        <ProdDBId>EPAXXXXX</ProdDBId>
        <ScanResults>
                <CommonVthData>
                        <COMMONTH>1</COMMONTH>
                        <CHI2_LIS desc=Fit Chi2>...</CHI2_LIS>
                        <GAIN_LIS desc=Fit Gain>...</GAIN_LIS>
                        <DAC_PE00 desc=PACIFIC Threshold Value V1 for PE00>...</DAC_PE00>
                        <DAC_PE05 desc=PACIFIC Threshold Value V1 for PE05>...</DAC_PE05>
                        <DAC_PE10 desc=PACIFIC Threshold Value V1 for PE10>...</DAC_PE10>
                        <DAC_PE15 desc=PACIFIC Threshold Value V1 for PE15>...</DAC_PE15>
                        <DAC_PE20 desc=PACIFIC Threshold Value V1 for PE20>...</DAC_PE20>
                        <DAC_PE25 desc=PACIFIC Threshold Value V1 for PE25>...</DAC_PE25>
                        <DAC_PE30 desc=PACIFIC Threshold Value V1 for PE30>...</DAC_PE30>
                        <DAC_PE35 desc=PACIFIC Threshold Value V1 for PE35>...</DAC_PE35>
                        <DAC_PE40 desc=PACIFIC Threshold Value V1 for PE40>...</DAC_PE40>
                        <DAC_PE45 desc=PACIFIC Threshold Value V1 for PE45>...</DAC_PE45>
                        <DAC_PE50 desc=PACIFIC Threshold Value V1 for PE50>...</DAC_PE50>
                </CommonVthData>
                <CommonVthData>
                        <COMMONTH>2</COMMONTH>
                        <CHI2_LIS desc=Fit Chi2>...</CHI2_LIS>
                        <GAIN_LIS desc=Fit Gain>...</GAIN_LIS>
                        <DAC_PE00 desc=PACIFIC Threshold Value V2 for PE00>...</DAC_PE00>
                        <DAC_PE05 desc=PACIFIC Threshold Value V2 for PE05>...</DAC_PE05>
                        <DAC_PE10 desc=PACIFIC Threshold Value V2 for PE10>...</DAC_PE10>
                        <DAC_PE15 desc=PACIFIC Threshold Value V2 for PE15>...</DAC_PE15>
                        <DAC_PE20 desc=PACIFIC Threshold Value V2 for PE20>...</DAC_PE20>
                        <DAC_PE25 desc=PACIFIC Threshold Value V2 for PE25>...</DAC_PE25>
                        <DAC_PE30 desc=PACIFIC Threshold Value V2 for PE30>...</DAC_PE30>
                        <DAC_PE35 desc=PACIFIC Threshold Value V2 for PE35>...</DAC_PE35>
                        <DAC_PE40 desc=PACIFIC Threshold Value V2 for PE40>...</DAC_PE40>
                        <DAC_PE45 desc=PACIFIC Threshold Value V2 for PE45>...</DAC_PE45>
                        <DAC_PE50 desc=PACIFIC Threshold Value V2 for PE50>...</DAC_PE50>
                </CommonVthData>
                <CommonVthData>
                        <COMMONTH>3</COMMONTH>
                        <CHI2_LIS desc=Fit Chi2>...</CHI2_LIS>
                        <GAIN_LIS desc=Fit Gain>...</GAIN_LIS>
                        <DAC_PE00 desc=PACIFIC Threshold Value V3 for PE00>...</DAC_PE00>
                        <DAC_PE05 desc=PACIFIC Threshold Value V3 for PE05>...</DAC_PE05>
                        <DAC_PE10 desc=PACIFIC Threshold Value V3 for PE10>...</DAC_PE10>
                        <DAC_PE15 desc=PACIFIC Threshold Value V3 for PE15>...</DAC_PE15>
                        <DAC_PE20 desc=PACIFIC Threshold Value V3 for PE20>...</DAC_PE20>
                        <DAC_PE25 desc=PACIFIC Threshold Value V3 for PE25>...</DAC_PE25>
                        <DAC_PE30 desc=PACIFIC Threshold Value V3 for PE30>...</DAC_PE30>
                        <DAC_PE35 desc=PACIFIC Threshold Value V3 for PE35>...</DAC_PE35>
                        <DAC_PE40 desc=PACIFIC Threshold Value V3 for PE40>...</DAC_PE40>
                        <DAC_PE45 desc=PACIFIC Threshold Value V3 for PE45>...</DAC_PE45>
                        <DAC_PE50 desc=PACIFIC Threshold Value V3 for PE50>...</DAC_PE50>
                </CommonVthData>
        </ScanResults>
</Entry>

<Entry>
        <Table>TH_CALIB_ASIC_LCLVTH</Table>
        <ProdDBId>EPAXXXXX</ProdDBId>
        <ScanResults>
        <ChData>
                <CH>0</CH>
                <LocalThData>
                        <LOCALTH>1</LOCALTH>
                        <CHI2_LIS desc=Fit Chi2>...</CHI2_LIS>
                        <GAIN_LIS desc=Fit Gain>...</GAIN_LIS>
                        <DAC_PE00 desc=PACIFIC Threshold Value V1 for PE00>...</DAC_PE00>
                        <DAC_PE05 desc=PACIFIC Threshold Value V1 for PE05>...</DAC_PE05>
                        <DAC_PE10 desc=PACIFIC Threshold Value V1 for PE10>...</DAC_PE10>
                        <DAC_PE15 desc=PACIFIC Threshold Value V1 for PE15>...</DAC_PE15>
                        <DAC_PE20 desc=PACIFIC Threshold Value V1 for PE20>...</DAC_PE20>
                        <DAC_PE25 desc=PACIFIC Threshold Value V1 for PE25>...</DAC_PE25>
                        <DAC_PE30 desc=PACIFIC Threshold Value V1 for PE30>...</DAC_PE30>
                        <DAC_PE35 desc=PACIFIC Threshold Value V1 for PE35>...</DAC_PE35>
                        <DAC_PE40 desc=PACIFIC Threshold Value V1 for PE40>...</DAC_PE40>
                        <DAC_PE45 desc=PACIFIC Threshold Value V1 for PE45>...</DAC_PE45>
                        <DAC_PE50 desc=PACIFIC Threshold Value V1 for PE50>...</DAC_PE50>
                </LocalThData>
                <LocalThData>
                        <LOCALTH>2</LOCALTH>
                        <CHI2_LIS desc=Fit Chi2>...</CHI2_LIS>
                        <GAIN_LIS desc=Fit Gain>...</GAIN_LIS>
                        <DAC_PE00 desc=PACIFIC Threshold Value V2 for PE00>...</DAC_PE00>
                        <DAC_PE05 desc=PACIFIC Threshold Value V2 for PE05>...</DAC_PE05>
                        <DAC_PE10 desc=PACIFIC Threshold Value V2 for PE10>...</DAC_PE10>
                        <DAC_PE15 desc=PACIFIC Threshold Value V2 for PE15>...</DAC_PE15>
                        <DAC_PE20 desc=PACIFIC Threshold Value V2 for PE20>...</DAC_PE20>
                        <DAC_PE25 desc=PACIFIC Threshold Value V2 for PE25>...</DAC_PE25>
                        <DAC_PE30 desc=PACIFIC Threshold Value V2 for PE30>...</DAC_PE30>
                        <DAC_PE35 desc=PACIFIC Threshold Value V2 for PE35>...</DAC_PE35>
                        <DAC_PE40 desc=PACIFIC Threshold Value V2 for PE40>...</DAC_PE40>
                        <DAC_PE45 desc=PACIFIC Threshold Value V2 for PE45>...</DAC_PE45>
                        <DAC_PE50 desc=PACIFIC Threshold Value V2 for PE50>...</DAC_PE50>
                </LocalThData>
                <LocalThData>
                        <LOCALTH>3</LOCALTH>
                        <CHI2_LIS desc=Fit Chi2>...</CHI2_LIS>
                        <GAIN_LIS desc=Fit Gain>...</GAIN_LIS>
                        <DAC_PE00 desc=PACIFIC Threshold Value V3 for PE00>...</DAC_PE00>
                        <DAC_PE05 desc=PACIFIC Threshold Value V3 for PE05>...</DAC_PE05>
                        <DAC_PE10 desc=PACIFIC Threshold Value V3 for PE10>...</DAC_PE10>
                        <DAC_PE15 desc=PACIFIC Threshold Value V3 for PE15>...</DAC_PE15>
                        <DAC_PE20 desc=PACIFIC Threshold Value V3 for PE20>...</DAC_PE20>
                        <DAC_PE25 desc=PACIFIC Threshold Value V3 for PE25>...</DAC_PE25>
                        <DAC_PE30 desc=PACIFIC Threshold Value V3 for PE30>...</DAC_PE30>
                        <DAC_PE35 desc=PACIFIC Threshold Value V3 for PE35>...</DAC_PE35>
                        <DAC_PE40 desc=PACIFIC Threshold Value V3 for PE40>...</DAC_PE40>
                        <DAC_PE45 desc=PACIFIC Threshold Value V3 for PE45>...</DAC_PE45>
                        <DAC_PE50 desc=PACIFIC Threshold Value V3 for PE50>...</DAC_PE50>
                </LocalThData>
        </ChData>

        ...

        <ChData>
                <CH>63</CH>
                <LocalThData>
                        <LOCALTH>1</LOCALTH>
                        <CHI2_LIS desc=Fit Chi2>...</CHI2_LIS>
                        <GAIN_LIS desc=Fit Gain>...</GAIN_LIS>
                        <DAC_PE00 desc=PACIFIC Threshold Value V1 for PE00>...</DAC_PE00>
                        <DAC_PE05 desc=PACIFIC Threshold Value V1 for PE05>...</DAC_PE05>
                        <DAC_PE10 desc=PACIFIC Threshold Value V1 for PE10>...</DAC_PE10>
                        <DAC_PE15 desc=PACIFIC Threshold Value V1 for PE15>...</DAC_PE15>
                        <DAC_PE20 desc=PACIFIC Threshold Value V1 for PE20>...</DAC_PE20>
                        <DAC_PE25 desc=PACIFIC Threshold Value V1 for PE25>...</DAC_PE25>
                        <DAC_PE30 desc=PACIFIC Threshold Value V1 for PE30>...</DAC_PE30>
                        <DAC_PE35 desc=PACIFIC Threshold Value V1 for PE35>...</DAC_PE35>
                        <DAC_PE40 desc=PACIFIC Threshold Value V1 for PE40>...</DAC_PE40>
                        <DAC_PE45 desc=PACIFIC Threshold Value V1 for PE45>...</DAC_PE45>
                        <DAC_PE50 desc=PACIFIC Threshold Value V1 for PE50>...</DAC_PE50>
                </LocalThData>
                <LocalThData>
                        <LOCALTH>2</LOCALTH>
                        <CHI2_LIS desc=Fit Chi2>...</CHI2_LIS>
                        <GAIN_LIS desc=Fit Gain>...</GAIN_LIS>
                        <DAC_PE00 desc=PACIFIC Threshold Value V2 for PE00>...</DAC_PE00>
                        <DAC_PE05 desc=PACIFIC Threshold Value V2 for PE05>...</DAC_PE05>
                        <DAC_PE10 desc=PACIFIC Threshold Value V2 for PE10>...</DAC_PE10>
                        <DAC_PE15 desc=PACIFIC Threshold Value V2 for PE15>...</DAC_PE15>
                        <DAC_PE20 desc=PACIFIC Threshold Value V2 for PE20>...</DAC_PE20>
                        <DAC_PE25 desc=PACIFIC Threshold Value V2 for PE25>...</DAC_PE25>
                        <DAC_PE30 desc=PACIFIC Threshold Value V2 for PE30>...</DAC_PE30>
                        <DAC_PE35 desc=PACIFIC Threshold Value V2 for PE35>...</DAC_PE35>
                        <DAC_PE40 desc=PACIFIC Threshold Value V2 for PE40>...</DAC_PE40>
                        <DAC_PE45 desc=PACIFIC Threshold Value V2 for PE45>...</DAC_PE45>
                        <DAC_PE50 desc=PACIFIC Threshold Value V2 for PE50>...</DAC_PE50>
                </LocalThData>
                <LocalThData>
                        <LOCALTH>3</LOCALTH>
                        <CHI2_LIS desc=Fit Chi2>...</CHI2_LIS>
                        <GAIN_LIS desc=Fit Gain>...</GAIN_LIS>
                        <DAC_PE00 desc=PACIFIC Threshold Value V3 for PE00>...</DAC_PE00>
                        <DAC_PE05 desc=PACIFIC Threshold Value V3 for PE05>...</DAC_PE05>
                        <DAC_PE10 desc=PACIFIC Threshold Value V3 for PE10>...</DAC_PE10>
                        <DAC_PE15 desc=PACIFIC Threshold Value V3 for PE15>...</DAC_PE15>
                        <DAC_PE20 desc=PACIFIC Threshold Value V3 for PE20>...</DAC_PE20>
                        <DAC_PE25 desc=PACIFIC Threshold Value V3 for PE25>...</DAC_PE25>
                        <DAC_PE30 desc=PACIFIC Threshold Value V3 for PE30>...</DAC_PE30>
                        <DAC_PE35 desc=PACIFIC Threshold Value V3 for PE35>...</DAC_PE35>
                        <DAC_PE40 desc=PACIFIC Threshold Value V3 for PE40>...</DAC_PE40>
                        <DAC_PE45 desc=PACIFIC Threshold Value V3 for PE45>...</DAC_PE45>
                        <DAC_PE50 desc=PACIFIC Threshold Value V3 for PE50>...</DAC_PE50>
                </LocalThData>
        </ChData>
        </ScanResults>
</Entry>

</ThCalibrationTables>

Calibration Plots

Section to be written by Lukas, Snow, ...

Charge Injection Scan

This scan aims at optimizing the PACIFIC comparator thresholds etc. etc. Snow/Lukas should continue with this.

WinCC Scan Configuration

The scan structure used by the DAQFEE WinCC code can be recognized by the automatically-produced scanrun.xml files stored in /calib/sf/ScanConfig. From the example below, one can recognize in the Option tag that the parameters being calibrated are etc etc to be written.

not yet found

The settings of each step are listed in the Step tag, as in the example below:

not yet found

Scan Data

describe counter data banks as in Olivier's note (Antonio or anyone else)

Data Analysis

The analysis code uses this data as input and tries to find the best value of the Charge Injection Delay and Charge Pulse CDC phase, i.e. those for which the number of bit errors is lowest. The goal of the analysis software is described in the /group/sf/etc/OnlineDB/ScanAnalysisSetup/CHARGE_TH_SCAN.xml file, a preliminary implementation of which is given below:

<ScanAnalysisSetup>
<RunType>CHARGE_TH_SCAN</RunType>

<ScanResults>
        <BoardType>EMB</BoardType>
        <Table>TH_CALIB_MB_DATAGBT</Table>
        <GBTData><GBT_N>0</GBT_N><ScanResult desc="Charge Injection Delay" ScanName="">CLKDEL1</ScanResult></GBTData>
        <GBTData><GBT_N>1</GBT_N><ScanResult desc="Charge Injection Delay" ScanName="">CLKDEL1</ScanResult></GBTData>
        <GBTData><GBT_N>2</GBT_N><ScanResult desc="Charge Injection Delay" ScanName="">CLKDEL1</ScanResult></GBTData>
        <GBTData><GBT_N>3</GBT_N><ScanResult desc="Charge Injection Delay" ScanName="">CLKDEL1</ScanResult></GBTData>
        <GBTData><GBT_N>4</GBT_N><ScanResult desc="Charge Injection Delay" ScanName="">CLKDEL1</ScanResult></GBTData>
        <GBTData><GBT_N>5</GBT_N><ScanResult desc="Charge Injection Delay" ScanName="">CLKDEL1</ScanResult></GBTData>
        <GBTData><GBT_N>6</GBT_N><ScanResult desc="Charge Injection Delay" ScanName="">CLKDEL1</ScanResult></GBTData>
        <GBTData><GBT_N>7</GBT_N><ScanResult desc="Charge Injection Delay" ScanName="">CLKDEL1</ScanResult></GBTData>
</ScanResults>

<ScanResults>
        <BoardType>ECB</BoardType>
        <Table>TH_CALIB_CB</Table>
        <ScanResult desc="Charge Pulse CDC phase" ScanName="">FPGA0_CHARGE_PULSE_PHASE</ScanResult>
        <ScanResult desc="Charge Pulse CDC phase" ScanName="">FPGA1_CHARGE_PULSE_PHASE</ScanResult>
</ScanResults>

<ScanResults>
        <BoardType>EPA</BoardType>
        <Table>TH_CALIB_ASIC</Table>
        <COMMONTH>1</COMMONTH><ScanResult desc=Fit Chi2>CHI2_Q</ScanResult>
        <COMMONTH>1</COMMONTH><ScanResult desc=Fit Gain>GAIN_Q</ScanResult>
        <COMMONTH>1</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V1 for Q00>DAC_Q00</ScanResult>
        <COMMONTH>1</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V1 for Q01>DAC_Q01</ScanResult>
        <COMMONTH>1</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V1 for Q02>DAC_Q02</ScanResult>
        <COMMONTH>1</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V1 for Q12>DAC_Q12</ScanResult>
        <COMMONTH>2</COMMONTH><ScanResult desc=Fit Chi2>CHI2_Q</ScanResult>
        <COMMONTH>2</COMMONTH><ScanResult desc=Fit Gain>GAIN_Q</ScanResult>
        <COMMONTH>2</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V2 for Q00>DAC_Q00</ScanResult>
        <COMMONTH>2</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V2 for Q01>DAC_Q01</ScanResult>
        <COMMONTH>2</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V2 for Q02>DAC_Q02</ScanResult>
        <COMMONTH>2</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V2 for Q12>DAC_Q12</ScanResult>
        <COMMONTH>3</COMMONTH><ScanResult desc=Fit Chi2>CHI2_Q</ScanResult>
        <COMMONTH>3</COMMONTH><ScanResult desc=Fit Gain>GAIN_Q</ScanResult>
        <COMMONTH>3</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V3 for Q00>DAC_Q00</ScanResult>
        <COMMONTH>3</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V3 for Q01>DAC_Q01</ScanResult>
        <COMMONTH>3</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V3 for Q02>DAC_Q02</ScanResult>
        <COMMONTH>3</COMMONTH><ScanResult desc=Common PACIFIC Threshold Value V3 for Q12>DAC_Q12</ScanResult>
</ScanResults>

<ScanResults>
        <BoardType>EPA</BoardType>
        <Table>TH_CALIB_ASIC_LCLVTH</Table>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=Fit Chi2>CHI2_Q</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=Fit Gain>GAIN_Q</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for Q00>DAC_Q00</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for Q01>DAC_Q01</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for Q02>DAC_Q02</ScanResult>
        <CH>0</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for Q12>DAC_Q12</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=Fit Chi2>CHI2_Q</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=Fit Gain>GAIN_Q</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for Q00>DAC_Q00</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for Q01>DAC_Q01</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for Q02>DAC_Q02</ScanResult>
        <CH>0</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for Q12>DAC_Q12</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=Fit Chi2>CHI2_Q</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=Fit Gain>GAIN_Q</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for Q00>DAC_Q00</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for Q01>DAC_Q01</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for Q02>DAC_Q02</ScanResult>
        <CH>0</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for Q12>DAC_Q12</ScanResult>

         ...

        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=Fit Chi2>CHI2_Q</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=Fit Gain>GAIN_Q</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for Q00>DAC_Q00</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for Q01>DAC_Q01</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for Q02>DAC_Q02</ScanResult>
        <CH>63</CH><LOCALTH>1</LOCALTH><ScanResult desc=PACIFIC Threshold Value V1 for Q12>DAC_Q12</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=Fit Chi2>CHI2_Q</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=Fit Gain>GAIN_Q</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for Q00>DAC_Q00</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for Q01>DAC_Q01</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for Q02>DAC_Q02</ScanResult>
        <CH>63</CH><LOCALTH>2</LOCALTH><ScanResult desc=PACIFIC Threshold Value V2 for Q12>DAC_Q12</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=Fit Chi2>CHI2_Q</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=Fit Gain>GAIN_Q</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for Q00>DAC_Q00</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for Q01>DAC_Q01</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for Q02>DAC_Q02</ScanResult>
        <CH>63</CH><LOCALTH>3</LOCALTH><ScanResult desc=PACIFIC Threshold Value V3 for Q12>DAC_Q12</ScanResult>
</ScanResults>

</ScanAnalysisSetup>

Calibration Results

The analysis results are stored in XML files; the structure of these XML files can be seen from the template file /group/sf/etc/OnlineDB/ScanResults/CHARGE_TH_SCAN.xml:

<ThCalibrationTables>
<RunType>CHARGE_TH_SCAN</RunType>
<RunNo>
        <NRuns>...</NRuns>
        <array name="list_of_run_no">
                <item>...</item>
                <item>...</item>
                ...
        </array>
</RunNo>

<Entry>
        <Table>TH_CALIB_MB_DATAGBT</Table>
        <ProdDBId>EMBXXXXX</ProdDBId>
        <ScanResults>
                <GBTData>
                        <GBT_N>0</GBT_N>
                        <CLKDEL1 desc="Charge Injection Delay" ScanName="">...</CLKDEL1>
                        <GBT_N>1</GBT_N>
                        <CLKDEL1 desc="Charge Injection Delay" ScanName="">...</CLKDEL1>
                        <GBT_N>2</GBT_N>
                        <CLKDEL1 desc="Charge Injection Delay" ScanName="">...</CLKDEL1>
                        <GBT_N>3</GBT_N>
                        <CLKDEL1 desc="Charge Injection Delay" ScanName="">...</CLKDEL1>
                        <GBT_N>4</GBT_N>
                        <CLKDEL1 desc="Charge Injection Delay" ScanName="">...</CLKDEL1>
                        <GBT_N>5</GBT_N>
                        <CLKDEL1 desc="Charge Injection Delay" ScanName="">...</CLKDEL1>
                        <GBT_N>6</GBT_N>
                        <CLKDEL1 desc="Charge Injection Delay" ScanName="">...</CLKDEL1>
                        <GBT_N>7</GBT_N>
                        <CLKDEL1 desc="Charge Injection Delay" ScanName="">...</CLKDEL1>
                </GBTData>
        </ScanResults>
</Entry>

<Entry>
        <Table>TH_CALIB_CB</Table>
        <ProdDBId>ECBXXXXX</ProdDBId>
        <ScanResults>
                <FPGA0_CHARGE_PULSE_PHASE desc="Charge Pulse CDC phase" ScanName="">...</FPGA0_CHARGE_PULSE_PHASE>
                <FPGA1_CHARGE_PULSE_PHASE desc="Charge Pulse CDC phase" ScanName="">...</FPGA1_CHARGE_PULSE_PHASE>
        </ScanResults>
</Entry>

<Entry>
        <Table>TH_CALIB_ASIC</Table>
        <ProdDBId>EPAXXXXX</ProdDBId>
        <ScanResults>
                <CommonThData>
                        <COMMONTH>1</COMMONTH>
                        <CHI2_Q desc=Fit Chi2>...</CHI2_Q>
                        <GAIN_Q desc=Fit Gain>...</GAIN_Q>
                        <DAC_Q00 desc=Common PACIFIC Threshold Value V1 for Q00>...</DAC_Q00>
                        <DAC_Q01 desc=Common PACIFIC Threshold Value V1 for Q01>...</DAC_Q01>
                        <DAC_Q02 desc=Common PACIFIC Threshold Value V1 for Q02>...</DAC_Q02>
                        <DAC_Q12 desc=Common PACIFIC Threshold Value V1 for Q12>...</DAC_Q12>
                </CommonThData>
                <CommonThData>
                        <COMMONTH>2</COMMONTH>
                        <CHI2_Q desc=Fit Chi2>...</CHI2_Q>
                        <GAIN_Q desc=Fit Gain>...</GAIN_Q>
                        <DAC_Q00 desc=Common PACIFIC Threshold Value V2 for Q00>...</DAC_Q00>
                        <DAC_Q01 desc=Common PACIFIC Threshold Value V2 for Q01>...</DAC_Q01>
                        <DAC_Q02 desc=Common PACIFIC Threshold Value V2 for Q02>...</DAC_Q02>
                        <DAC_Q12 desc=Common PACIFIC Threshold Value V2 for Q12>...</DAC_Q12>
                </CommonThData>
                <CommonThData>
                        <COMMONTH>3</COMMONTH>
                        <CHI2_Q desc=Fit Chi2>...</CHI2_Q>
                        <GAIN_Q desc=Fit Gain>...</GAIN_Q>
                        <DAC_Q00 desc=Common PACIFIC Threshold Value V3 for Q00>...</DAC_Q00>
                        <DAC_Q01 desc=Common PACIFIC Threshold Value V3 for Q01>...</DAC_Q01>
                        <DAC_Q02 desc=Common PACIFIC Threshold Value V3 for Q02>...</DAC_Q02>
                        <DAC_Q12 desc=Common PACIFIC Threshold Value V3 for Q12>...</DAC_Q12>
                </CommonThData>
        </ScanResults>
</Entry>

<Entry>
        <Table>TH_CALIB_ASIC_LCLVTH</Table>
        <ProdDBId>EPAXXXXX</ProdDBId>
        <ScanResults>
        <ChData>
                <CH>0</CH>
                <LocalThData>
                        <LOCALTH>1</LOCALTH>
                        <CHI2_Q desc=Fit Chi2>...</CHI2_Q>
                        <GAIN_Q desc=Fit Gain>...</GAIN_Q>
                        <DAC_Q00 desc=PACIFIC Threshold Value V1 for Q00>...</DAC_Q00>
                        <DAC_Q01 desc=PACIFIC Threshold Value V1 for Q01>...</DAC_Q01>
                        <DAC_Q02 desc=PACIFIC Threshold Value V1 for Q02>...</DAC_Q02>
                        <DAC_Q12 desc=PACIFIC Threshold Value V1 for Q12>...</DAC_Q12>
                </LocalThData>
                <LocalThData>
                        <LOCALTH>2</LOCALTH>
                        <CHI2_Q desc=Fit Chi2>...</CHI2_Q>
                        <GAIN_Q desc=Fit Gain>...</GAIN_Q>
                        <DAC_Q00 desc=PACIFIC Threshold Value V2 for Q00>...</DAC_Q00>
                        <DAC_Q01 desc=PACIFIC Threshold Value V2 for Q01>...</DAC_Q01>
                        <DAC_Q02 desc=PACIFIC Threshold Value V2 for Q02>...</DAC_Q02>
                        <DAC_Q12 desc=PACIFIC Threshold Value V2 for Q12>...</DAC_Q12>
                </LocalThData>
                <LocalThData>
                        <LOCALTH>3</LOCALTH>
                        <CHI2_Q desc=Fit Chi2>...</CHI2_Q>
                        <GAIN_Q desc=Fit Gain>...</GAIN_Q>
                        <DAC_Q00 desc=PACIFIC Threshold Value V3 for Q00>...</DAC_Q00>
                        <DAC_Q01 desc=PACIFIC Threshold Value V3 for Q01>...</DAC_Q01>
                        <DAC_Q02 desc=PACIFIC Threshold Value V3 for Q02>...</DAC_Q02>
                        <DAC_Q12 desc=PACIFIC Threshold Value V3 for Q12>...</DAC_Q12>
                </LocalThData>
        </ChData>

        ...

        <ChData>
                <CH>63</CH>
                <LocalThData>
                        <LOCALTH>1</LOCALTH>
                        <CHI2_Q desc=Fit Chi2>...</CHI2_Q>
                        <GAIN_Q desc=Fit Gain>...</GAIN_Q>
                        <DAC_Q00 desc=PACIFIC Threshold Value V1 for Q00>...</DAC_Q00>
                        <DAC_Q01 desc=PACIFIC Threshold Value V1 for Q01>...</DAC_Q01>
                        <DAC_Q02 desc=PACIFIC Threshold Value V1 for Q02>...</DAC_Q02>
                        <DAC_Q12 desc=PACIFIC Threshold Value V1 for Q12>...</DAC_Q12>
                </LocalThData>
                <LocalThData>
                        <LOCALTH>2</LOCALTH>
                        <CHI2_Q desc=Fit Chi2>...</CHI2_Q>
                        <GAIN_Q desc=Fit Gain>...</GAIN_Q>
                        <DAC_Q00 desc=PACIFIC Threshold Value V2 for Q00>...</DAC_Q00>
                        <DAC_Q01 desc=PACIFIC Threshold Value V2 for Q01>...</DAC_Q01>
                        <DAC_Q02 desc=PACIFIC Threshold Value V2 for Q02>...</DAC_Q02>
                        <DAC_Q12 desc=PACIFIC Threshold Value V2 for Q12>...</DAC_Q12>
                </LocalThData>
                <LocalThData>
                        <LOCALTH>3</LOCALTH>
                        <CHI2_Q desc=Fit Chi2>...</CHI2_Q>
                        <GAIN_Q desc=Fit Gain>...</GAIN_Q>
                        <DAC_Q00 desc=PACIFIC Threshold Value V3 for Q00>...</DAC_Q00>
                        <DAC_Q01 desc=PACIFIC Threshold Value V3 for Q01>...</DAC_Q01>
                        <DAC_Q02 desc=PACIFIC Threshold Value V3 for Q02>...</DAC_Q02>
                        <DAC_Q12 desc=PACIFIC Threshold Value V3 for Q12>...</DAC_Q12>
                </LocalThData>
        </ChData>
        </ScanResults>
</Entry>

</ThCalibrationTables>

Calibration Plots

Section to be written by Lukas, Snow, ...

-- LukasWitola - 2022-11-01

Topic attachments
I Attachment History Action Size Date Who Comment
JPEGjpg DataTakingAnalysis.jpg r1 manage 132.2 K 2022-10-07 - 17:47 AntonioPellegrino  
JPEGjpg FE-Calibration-Sequence.jpg r1 manage 103.6 K 2022-10-01 - 10:45 AntonioPellegrino  
PDFpdf FeTimingCalibration.pdf r1 manage 81.1 K 2022-09-16 - 10:16 AntonioPellegrino  
JPEGjpg ScanDiagram-RevisedbyFederico-Jun2022.jpg r1 manage 132.6 K 2022-10-28 - 12:58 AntonioPellegrino  
PDFpdf ScanDiagram-RevisedbyFederico-Jun2022.pdf r1 manage 143.4 K 2022-10-28 - 12:54 AntonioPellegrino  
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