Description of the hardware and software setup

The Calo test rack

The calo test rack is located in 2885 2-0001 (2nd floor above the control room at the pit).

The relevant part for the Herschel test setup are the PC with specs server (lbcalospecs01) which has CAT and PVSS (PVSS newer version to be installed), and the 9U crate containing the FE board and the CROC.

One FE is located on slot 6 which correspond to FE 4 for the CROC and the other one is located on slot 14 corresponding to FE11 for the CROC. The PC is the specs master and is connected to the CROC via an ethernet cable, allowing configuration and control of the boards.

Configuration of the board can be achieved via CAT software (on lbcalospecs01) and should be implemented in PVSS. Tests (read/write RAMs) can be performed using CAT.

Power on the crate

The crate is powered by a Wiener power supply.


To power on the crate, hold the "power" red button of the wiener on the "on" position until it is started (takes few seconds). To power off the crate press down the power button on the "off" position until is turns off. DO NOT leave the crate powered when not performing tests (ie if you leave the pit)


The CAT application implement the ECS of the Calo boards (just like PVSS), but also offers the possibility to read/write RAMs, access the spy FPGA etc... It also allow to implement automated test procedures. The lbcalospecs01 pc which is located on the top of the rack is accessible from the cern network (no need to go through lbgate), has CAT installed and is connected to the test bench.

Main Panel and Tree Panel

The main panel of the CAT application allows to charge the configuration of a crate (for the test set-up under CATLAL/cdf/HerschelDev.cdf) and perform some predefined tests (not explored yet for Herschel).


The tree panel draw the SPECS elements. It allows to access the configuration of the slaves (CROC and FE in particular)


Configuration Panels (CROC , FE and TVB)

The configuration panel of the CROC allow to setup most of the option related to test data aquisition. In the following figure, the main control are detailed


The configuration panel of the front end board allow to configure the FE related options (delay, pedestal subtraction, sampling clock), but also has a spy functionality at the Seq PGA output and allow to load RAM in the FEPGA (fake ADC values), or to generate pulses as input of the board. In the following figure, the main control are detailed




Crate configuration file

cd /
new VMEAdapter VMEBus
cd /VMEBus
  new TTCvi TTCvi
cd /
Define the specs master
new SpecsMaster Master
cd /Master
  . Device 1
  . Port 1
Add the CROC as a slave. The CROC adress is hard coded since it is always at the same location in the crate (fixed by the backplane design)
cd /Master
  new CROC Croc
Add the FEB as slaves.
cd /Master
  new FEB_XCAL Feb4
  new FEB_XCAL Feb11
Define the slot for the FEB (Slot 6 or 14 in our case), the firmware in the FPGA (XCAL_v2), and the adress of the Glue (send the ECS signals? to check) which correspond to the slot number
cd /Master/Feb4
    . XCAL_v2
    . Slot 6
    cd /Master/Feb4/Glue
      . Address 6
   cd /Master/Feb11
    . XCAL_v2
    . Slot 14
    cd /Master/Feb11/Glue
      . Address 14
Set low speed for the specs server to avoid problems
cd /Master
  . Speed 3
Configure the CROC
cd /Master/Croc
    . reset  
    . ClockInput 0
    . TTCrq 0 0
    . Synchro 16 20
    . InvClk 1 1 1 1
    . ClockDiv 4000000
    . NDump  0
    . NSpy   10
    . NL0     10
    . L0Freq  0
    . L0Delay 11
    . ChannelB 00000000 00000000 00000000 00000000	
. fepga 0 0 0 0 0
. fepga 1 1 0 0 0
. fepga 2 0 0 0 1
. fepga 3 0 0 0 0
. feb 0 1 8 0
cd /Master/Feb4
  inc CATLAL/cdf/FEB-XCAL.cdf
cd /Master/Feb11
  inc CATLAL/cdf/FEB-XCAL.cdf



-- VictorCoco - 03 Oct 2014
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Topic revision: r2 - 2014-10-03 - VictorCoco
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