The actual test

1. Provide yourself with a test sheet for the slot you want to test.
2. Check the already connected cables and establish the missing connections.
3. Perform the digitisation delay scan.
4. Analyse the data and derive the optimal timing.
5. Apply the new settings to the TELL1.
6. Perform the cable test
7. Take a data file with test pulses.
8. Take a data file without test pulses.
9. Analyse the data.
10. Turn off the Beetles and the Repeater Board if no further investigations are necessary.
11. Fill in the test sheet.
12. Leave an entry with all the results in the ELOG: http://lbweb01.cern.ch/Velo+PCB+tests.

Detailed explanations

1. Check and connectorisation of the cables
2. PVSS operation of the system
3. Running the eventbuilder
4. Digitisation delay scan
5. Data analysis

In case of problems

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