The LHCb Upgrade Silicon Strip Common ASIC - SALT (Silicon ASIC for LHCb Tracking)


SALT general description

Silicon strip detectors in the upgraded Tracker of LHCb experiment will use a new 128-channel readout ASIC called SALT. A block diagram of the SALT is shown in figure below. SALT extracts and digitizes analogue signals from the sensor, performs digital processing and transmits a serial output data. It is designed in TSMC CMOS 130 nm technology, and uses a novel architecture comprising an analogue front-end and an ultra-low power (< 0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel.

SALT block diagram

Estimated power consumption at 1.2V power supply:

Block Power N Total
Analog 2.5mW 128 320mW
Digital 3.16mW 128 405mW
ASIC 5.66mW 128 725mW


SALT tests


Other important events

SALT Publications and Conferences

Topic attachments
I Attachment History Action Size Date Who Comment
PDFpdf salt_3_pads.pdf r1 manage 431.6 K 2018-10-11 - 16:32 TomaszFiutowski SALT3 Padring
Texttxt salt_3_pads.txt r1 manage 8.8 K 2018-10-11 - 16:34 TomaszFiutowski SALT3 Pads coordinates
SVG (Scalable Vector Graphics)svg salt_block.svg r2 r1 manage 80.3 K 2018-07-05 - 14:37 KrzysztofSwientek  
PDFpdf salt_v3_spec.pdf r4 r3 r2 r1 manage 2090.6 K 2016-12-22 - 14:16 MarekIdzik SALT - documentation of 128-channel ASIC for UT readout, updated 22/12/2016
PDFpdf salt_v4_spec.pdf r4 r3 r2 r1 manage 1533.0 K 2018-05-29 - 17:01 KrzysztofSwientek Documentation of 2nd 128-channel SALT version
PDFpdf salt_v5_spec.pdf r3 r2 r1 manage 1716.1 K 2018-12-11 - 09:27 KrzysztofSwientek SALT3 documentation
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Topic revision: r36 - 2018-12-11 - KrzysztofSwientek
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