Produces monitoring histograms for checking silicon simulation.

Produces an ouptut table when running boole.

This monitors the MCVeloFE (front-end) objects, which store the charge in electrons simulated in each Velo channel above threshold.

Code is in the VeloSimulation package


Produces monitoring histograms for checking FPGA algorithm emulation.

Produces an ouptut table when running boole / vetra.

This monitors the VeloDigit objects, which store the ADC values of each Velo channel.

In the simulation only channels above a threshold are kept, in the non-zero suppressed data all channels are present.

Code is in the VeloAlgorithms package.

-- Main.parkes - 24 Mar 2006

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Topic revision: r1 - 2006-03-24 - ChrisParkes
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