pALPIDE-3 Digital Verification Tracking


Relevant Links

ITS-WP3

Environment Development

Setup

  • DONE Changes to comply with modifications to top_registers. This includes READOUT MODE A & B to triggered & continuous, bypass, dmu_cfg registers (dmusettings addr 6-16, cmudmusetreg addr 6-9)

Discussion on priority

  • Deliver a tb with a single chip (IB) to enable most effective simulations of all internal chip functions -- GianlucaAglieriRinella - 2015-03-10

Scoreboard

Readout Monitor

  • DONE Change to new protocol monitoring for both monitor and stream_monitor - needs verification
  • DONE verification of data stream monitor, working

Assertion Checks for internal wiring

  • DONE check wiring of top _register to FROMU, DMU, DTU etc.
  • IN PROGRESS check encoding of analogue input encoding

BFM

  • DONE Propagation of bypass setting to BFM for dual mode simulation
  • DONE Assertion for code_error checks
  • DONE Update protocol checker to match new protocol. - The protocol checker needs verification and simulation (awaiting new blocks)
  • DONE Modify stream monitor tasks for pALPIDE3. - The tasks need to be verified with a simulation.

Assertions

  • DONE A checker to see that busy_off is always sent within 2 cycles of busy_on
  • DONE Assertion to ensure there no two busy_on words written in sequence
  • DONE Assertion to ensure decoder only receives legal bytes

Functional Coverage Implementation

Matrix Coverage

  • Done Matrix Data Coverage, corner regions, encoders
  • DONE Coverage of CHIP HDR + TRAILER received and cross with frame size (should not receive a frame size =0 + chip hdr/trl) - SvetlomirHristozkov - 2015-03-04
  • DONE Matrix frame flags coverage -- SvetlomirHristozkov - 2015-03-04

BFM Coverage

  • TO DO Coverage of delay between BUSY_OFF and BUSY_ON
  • TO DO Coverage of the use of protocol word used

DCTRL Coverage

  • DONE Coverage of transactions tested - reset, GRST, PRST, WRITE, READ, MULTICAST etc.
  • DONE Coverage of locations written to. locations read from.
  • DONE Coverage of write/read to self-resetting registers (periphery control bit 4 for example)

CONFIG Coverage

  • DONE Coverage of INNER MODE/OUTER Mode
  • DONE Coverage of enabled chips (in OUTER Mode)

Matrix Behavioural Model

  • DONE Ensure compatibility with matrix_top interface definition for implementation - reflect latest interface changes
  • DONE Replace the pulse type/regsel functionality with apulse/dpulse and maskreg_rowsel/pulsereg_rowsel
  • TO DO Assertion checks to ensure that buffering is correct i.e. first 512 lines of MEMSEL_B are the same, second 512 lines of MEMSEL are the same etc. Same for STROBE_B, FLUSH_B, APULSE, DPULSE
  • DONE implement new PE addressing - SvetlomirHristozkov - 2015-03-03

Utilisation

Scripts and Makefile

  • Done Modify Makefile build_rtl utility to take file list as an input and compile that
  • Done Generate two sets of file inputs - 1 for verification & development and 1 for top level implementation/interface checking
  • Done Create filelist generation scripts
  • Done Reorganise source tree
  • DONEImplement distributed compilation option to speed up sims - i.e. no need to recompile/re-elaborate the sources that are unlikely to change (RTL)
  • DONE Add option for simulation profiling - needed to improve simulation time (which worsened following addition of encoding/decoding)

Test Definition

Integrated chip signoff checks

  • DONE Measure min duration of FLUSH_B. Measure delay between MEMSEL_B assertion and start of readout to RRUs.
    • FLUSH_B generation reviewed and fixed in latest FROMU iteration. On PRST command it is made 10 clk cycles long. When made in Continuous Mode it is asserted until feedback from the RRUs stating completion of Matrix readout is received.
    • The RRUs sample the VALID outputs two clk cycles after the launching of the MEMSEL_B signal.
  • ONGOING Analise and check propagation of global digital signals (STROBE_B, MEMSEL_B, FLUSH_B) trough the PE, delays and strengths (PE gate level annotated sims).
  • DONE Direct checking of validity of fanout logic and wiring to PE ports of STROBE_B and MEMSEL_B signals (interleaving on the array; probably already checked by top sim however direct wave diagram analysis very easy)
  • DONE Verification of BUSY handling features of FROMU (sim with EN_BUSY_MON = 1).
  • DONE Configuration scenarios: triggered mode disabling columns or regions or disabling individual MEB banks.
  • TODO Test of transmission of special (busy violation flag set) chip data frame(s) on busy violation condition in triggered mode.
  • WON'T DO Testing of continuous mode readout.
  • DONE Measurement of dead time and trigger losses under WP10 readout conditions.
  • DONE [Svet, Davide] Analyze (and possibly waive) the warning messages generated by the mem model.
  • DONE Sim run with post pnr netlist of digital_top.
    • Done with sdf max delays until now. (Consider trying min/typ model)
  • ONGOING Timing of interface with Matrix, PEs and Pixels.
    • Manual Static Timing Analysis.
    • DONE Verify driving capabilities of ADDRESS outputs from Matrix against estimated load.
    • ONGOING Gate-level sims of digital_top and PEs and Digital Pixel (at least for a subset of columns).
  • DONE Timing of interfaces on local DATA bus and inter-chip data exchange with timing.
    • DONE Dedicated verification of DDR timing
    • DONE Dedicated study of transition of token and timing of drivers disabling/enabling.
  • DONE Timing of R/W accesses to DPRAM blocks from CMU (check validity of multi-cycle path constraint).
    • Produce timing diagram of read and write cycles with CMU and DPRAM ports signals, identify active clock edges, analyze validity of sdc constraint on these arcs.
  • DONE Check wiring, polarity and initialization of global reset, Power-on-Reset, Power-on-Reset disable signals, Global Reset command. DM 03.06.2015
  • DONE Check post-reset and post power-on input pin values of all MLVDS transceiver blocks. Check valid default current DAC settings, output enable, on chip term resistors enabling for all the target scenarios (INNER, OB Master, OB Slave). DM 11.05.2015
Signal INNER MASTER SLAVE (ID<6) SLAVE (ID=6)
MCLK_EN_RECEIVER 0 1 0 0
MCLK_EN_DRIVER 0 0 0 0
MCLK_DAC_RECEIVER hA hA hA hA
MCLK_DAC_DRIVER 0 0 0 0
MCLK_TERM_RES_EN 0 0 0 0
DCLK_EN_RECEIVER 1 1 1 1
DCLK_EN_DRIVER 0 1 0 0
DCLK_DAC_RECEIVER hA hA hA hA
DCLK_DAC_DRIVER hA hA hA hA
DCLK_TERM_RES_EN 0 1 0 1
DCTRL_EN_RECEIVER 1 1 0 0
DCTRL_EN_DRIVER 0 0 0 0
DCTRL_DAC_RECEIVER hA hA hA hA
DCTRL_DAC_DRIVER hA hA hA hA
DCTRL_TERM_RES_EN 0 0 0 0
BUSY_OE_N 1 1 1 1
DATAOUT_OE_N 1 1 1 1
CNTRL_OE_N 1 0 1 1
  • DONE Check post-reset and post power-in values for all input ports of DTU block. Check polarity of PLL enabling and reset signals. DM 11.05.2015
Signal INNER MASTER SLAVE
DTU_DATA_O h2358D635 h3803F1C7 h3803F1C7
(2nd word on IB) h17CA0D7C - -
DTU_DRVDAC h8 h8 h8
DTU_LOAD_EN 0 0 0
DTU_PLLCFG hD hD hD
DTU_PLLDAC h8 h8 h8
DTU_PLL_CLK40 CLK40 CLK40 CLK40
DTU_PLL_RST 0 0 0
DTU_PREDAC 0 0 0
DTU_SERPHASE h8 h8 h8
DTU_SER_CLK40 CLK40 CLK40 CLK40
DM note: DTU_PLL_LOCK (input to digital_top), is NOT asserted.

-- GianlucaAglieriRinella - 2015-06-04

Topic attachments
I Attachment History Action Size Date Who Comment
PDFpdf PE_Padre_propagation_delays_-_Prop_delays_Timing_Analysis.pdf r1 manage 66.6 K 2015-05-19 - 18:20 GianlucaAglieriRinella Report on propagation delays of Priority Encoder (also known as PE/Padre/Encoxtop ...)
Unknown file formatxlsx verification_specs.xlsx r1 manage 17.6 K 2015-03-30 - 15:07 SvetlomirHristozkov Verification Excel Specifications
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Topic revision: r25 - 2016-05-16 - GianlucaAglieriRinella
 
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