TDR description

A small introduction

TDR stands for "Tracker Data Reduction". The TDR is the circuit which:

  1. acquires the signals from the silicon ladders,
  2. digitizes them,
  3. analyzes them,
  4. transmits the processed data to a higher acquisition level (namely the Jinf).

There are three analysis processes:

  1. Pedestal calibration.
  2. Gain calibration.
  3. Data reduction.

To do a data reduction, a pedestal calibration is mandatory...

The TDR2 board


To make things "easy and self explaining", the board hosting the TDR circuit is called TDR2. Why a 2 ? Because it is actually hosting two TDR circuits. Thus a TDR2 board is connected to two silicon modules. Strangely enough, the TDR2 board is often misnamed "TDR".

Following picture shows the main components of a single TDR circuit:

The key elements in the TDR circuit are an FPGA (Actel A54SX32A) and a DSP (Analog Devices ADSP 2187, instruction set). There are three ADCs, two dedicated to the S-side (S1 and S2, each one reading out 320 channels), and one dedicated to the K-side (K, reading out 384 channels).

Data acquisition modes

The simplest acquisition mode is the raw data mode, i.e. no data reduction is done. In such a case, all the 1024 silicon channels are transmitted to the Jinf.

  • Event size = 2050 bytes (1025 words of 16 bits).
  • Event format =Event_number, S01, S02,K0 , S11, S12, K1, S3191, S3192, K319, K320 , ... , K383. The bits are shifted by three positions, so you will have to make a "shift right" of three positions to get the correct ADC value. Note the S1-S2-K structure: this is due to the fact that the three ADCs are read in parallel.

In reduced or compressed data mode, only selected groups of channels ("clusters") are transmitted:

  • Variable event size.
  • Event format = Event_number, (length-1), first, adcfirst, adcfirst+1, ... , adcfirst+(length-1) , (length-1) , first, ... Here, the 'adc' values are signed short int, and you will have to divide them by 8.0 to get the correct value. 'first' corresponds to the index of the first channel composing the cluster. An index from 0 to 639 corresponds to a cluster on the S-side, an index from 640 to 1023 corresponds to a cluster on the K-side. The "length-1" and "first" words actually hold more information than just the cluster size and position. See the DSP code documentation for a detailed description.
  • Optionnally (for debugging purposes), at the end of the reduced event, the common noise values computed for the 16 VAs are given. Here, the common noise values are signed short int, and you will have to divide them by 8.0 to get the correct value.

Each value is one word of 16 bits.

A particular reduction mode has been introduced for the TAS acquisitions. In such a case, clusters with fixed origin and length are produced, see DSP code documentation.

In the case of the mixed mode, the event is composed of both raw and reduced data, raw data being followed by the reduced data.

Some numbers

  • The trigger to hold time is different for S- and K- sides: TTHK=TTHS+0.9 s (png).
  • DSP clock frequency 25 MHz. Instruction cycle rate is twice the clock frequency, i.e. 50 MHz. Thus a cycle takes 20 ns.
  • Channel readout frequency (clock ADCs): 5 MHz., i.e. 200 ns per channel.
  • Interrupt frequency (for IDLE command): 50 kHz i.e. 20 s per IDLE instruction.

Some measurements

According to the TDR2 schematics, the FPGA provides an unique HCCSTB (strobe) signal, sent to the S and K sides, the same for CLKADC.

  • Strobe S and K signals: (png).
  • Readout sequence, hold and strobe on S-side: (png), detail (png), finer detail (png)
  • Hold and strobe K: (png)
  • Begin of readout sequence, with hold, strobe and clock adc: (png)
  • End of readout sequence, with hold, strobe and clock adc. Note that for the last VA, 71 strobe signals are sent: (png)

The ADC stage

The ADC works in the mode described in figure 9 page 11 of the data sheet. Namely, the conversion is performed in a range 2Vref around the voltage set at IN, in our case Vref itself. According the data sheet, Vref is defined by a set of two resistances (R189 and R29 in the following design):

Here, Vref = (1 + R189 / R29) = 1.83 V. Thus an ADC unit corresponds to 2*1.83/4095=0.00089 V.

Let us now focus on the amplification stage:

The following is based on E. Cortina's document you can find here. The signal at the output of the operational amplifier, and the pedestal level, are expressed as:

With the values set in the circuit, the factor of V-out is -1, while the factor of V+out is 0.99 . Regarding the pedestal value, as an example, on a TDR, a voltage of 0.370 V has been measured at the output of the amplifier (acquisition was stopped of course...). Thus this corresponds the theoretical value of 0.369 V, corresponding to 413 ADC. Here you can find another description of the amplification stage.

DAC calibration

The DAC calibration consists in sending a step voltage to a reference capacitance of 2pF on the VA. The charge thus deposited is sent to a selected channel, and a sampling as a function of time is thus possible. The ACTEL takes care of setting the VAs in the TEST mode. Then, each channel of each ADC group is tested in sequence (S1, S2, K). The sampling is performed at 4 s on the S-side, and at 5 s on the K-side. The DAC circuit is represented here, for the S-side:

As we can see, depending on the state of the B0, B1 and B2 bits, the current will be I=1.6mA*(B0+2*B1+4*B2). As on the hybrid the CAL line is terminated with a 50 Ohm resistor, the voltage applied on the test capacitor will be V=80mV*(B0+2*B1+4*B2). As a consequence, the charge released on the capacitors (remember, two VAs (S1 and S2) are tested at the same time) will be, for each capacitor:

DAC Charge (106 e) MIP Z
1 1 43 6.6
2 2 87 9.3
3 3 130 11.4
4 4 174 13.2
5 5 217 14.7
6 6 261 16.1
7 7 304 17.4

For the K-side, the resistors are four times higher, thus the currents are four times lower. Thus V=20mV*(B0+2*B1+4*B2). We have the following table:

DAC Charge (106 e) MIP Z
1 0.25 10.9 3.3
2 0.50 21.7 4.7
3 0.75 32.6 5.7
4 1.00 43.4 6.6
5 1.25 54.3 7.4
6 1.50 65.1 8.1
7 1.75 76.0 8.7

Those values, though remain quite theoretical. For instance, measurements were done on S-side of circuit A of QM2 TDR 92002. Taking into account the real resistance values (R112=1000 Ohm, R114=511 Ohm, R116=240 Ohm) and the following measured transistor voltages levels:

  • V2 (Q9) = 3.18 V
  • V2 (Q10) = 3.22 V
  • V2 (Q11) = 3.30 V
  • V3 (Q21) = 665 mV
  • V3 (Q25) = 666 mV
  • V3 (Q26) = 666 mV

we find following values, which are in good agreement with the measurements:

DAC Vdac expected (mV) Vdac measured (mV)
1 91 92
2 174 175
3 265 265
4 354 350
5 445 440
6 528 516
7 619 612

The time needed is a bit less than 81 milliseconds: the measurement shown here includes also some DSP operations. Data sheets: MMBT3904, MMBT3906.

TDR2 Test points

There is one test point (TP32 for upper half and TP33 for lower half) which is connected to pin 87 (flag FL0) of the DSP. In the code, it then possible to SET/RESET/TOGGLE the output signal of that pin to proceed to flow control. In the assembler code, just type one of those:

  • SET FL0


TDR2 files

  • Schematics
  • Mounting
  • Layers

-- PhilippAzzarello - 23-Aug-2010

Topic attachments
I Attachment History Action Size Date Who Comment
PDFpdf ADS803.pdf r1 manage 255.8 K 2010-08-23 - 15:50 PhilippAzzarello ADC data sheet
PDFpdf MMBT3904.pdf r1 manage 111.3 K 2010-08-23 - 15:56 PhilippAzzarello  
PDFpdf MMBT3906.pdf r1 manage 97.5 K 2010-08-23 - 15:56 PhilippAzzarello  
PDFpdf actelTDR.pdf r1 manage 415.9 K 2010-08-23 - 15:41 PhilippAzzarello FPGA data sheet
PDFpdf ampli2.pdf r1 manage 70.5 K 2010-08-23 - 13:50 PhilippAzzarello Calculations to get to the TDR pedestal expressions
PDFpdf dspTDR.pdf r1 manage 223.2 K 2010-08-23 - 15:43 PhilippAzzarello TDR DSP data sheet
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Topic revision: r6 - 2010-09-07 - PhilippAzzarello
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