Adding custom peripherals (to the Microblaze)

This reflects some of the experience trying to do this with the picoblaze frequency counter.

  • remove the LED, switch and LCD lines, leave only the input/output port data and register address, clock, reset, read/write strobes, interrupt and interrupt acknowledge.

  • when importing a peripheral
    • in the dialog 'Import Peripheral - Name and Version' one must use the name of the top level entity as used in the vhdl file specified later (e.g. frequency_counter).


Considered the following buses to interface the frequency counter to the microblaze:

FSL (fast simplex link)

  • Seems to have fifos (useful for crossing clock domains) but I don't find any means of addressing registers (i.e. to me this looks suitable for devices which stream data into the processor or read streams from the processor).
  • See e.g. the FSL data sheet, application note 529. Note also that one needs one link for each direction (as the name says).

DCR (Device Control Register Bus)

  • See e.g. the description from Xilinx.
  • Looks like the DCR bus is the easiest bus to interface the frequency counter to.
  • see the xilinx documentation here, and the reference documentation at IBM (e.g. page 22 for the meaning of the read and write signals on the slave side).

  • Seems that the generated peripheral however is NOT available to be connected to the microblaze, only PowerPC shows up in the list of supported platforms... Even adding Microblaze by hand (with a text editor), I couldn't add this generate peripheral to the list of devices...

PLB (Processor Local Bus)

  • With this bus, it's easiest to create a new peripheral (as opposed to import an existing one). This will also create an example which can then be used to paste the relevant code of the frequency counter into it.
  • The addressing logic in the example is 'already decoded', i.e. one gets one line per register.


  • the SMA pin seems to be A10, the IO-standard LVTTL.
  • The board definition file for the board we're using seems to be $XILINX_EDK\board\Xilinx\boards\Xilinx_Spartan3E_RevD\data\Xilinx_Spartan3E_RevD_v2_2_0.xbd .
  • The files for the IP cores seem to be in $XILINX_EDK\hw\XilinxProcessorIPLib\pcores .
  • for a generated pcore, there seems to be a ISE project file generated which is in pcores\_\devl\projnav\.ise.
  • There is a wrapper generated in hdl\_0_wrapper.vhd. Note that the external inputs (such as sma_clk) are not automatically generated there, this needs to be defined in pcores\_\data\_.mpd with a line like the following:
   PORT SMA_CLK = "", DIR = I
  • Once this is done, in the 'system assembly view', this pin should appear under (if necessary, restart EDK). One can then select 'make external' from the pull down menu.
  • Only after that has been done, one should see a corresponding pin in the (generated, by platgen ?) file hdl\<project_name>.vhd the next time the project is built (generation of the bistream file).
  • The pin in the top level design (?) (which is hdl\<project_name>.vhd), is called <name_of_peripheral>_<instance>_sma_clk_pin. This name should be used in the user constaints file data\<project_name&gt.ucf.
  • To generate the base address of the custom peripheral, I had to go to the 'Addresses' Tab in EDK, choose a 'Size' (e.g. 1k) and click on the 'Generate Addresses' button on the top right. I then got an address range 0x86a08000..0x86a083ff .


  • The address of the PLB peripheral


-- AndreHolzner - 29 Sep 2008

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Topic revision: r7 - 2008-10-08 - AndreHolzner
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