• Rev 3F board from new batch.
  • Sent to CERN on 28 Oct 2008
  • from September 2015 to 09.06. in Pixel HW development crate in SR1 (pixrcc01 or pixrcc07)
  • no issues with TTC clock (no fine adjustment needed) but the "breaking TIM" problem, cured from FW#0x5a
  • equipped with TTCrq plugin V5000812237075001114 (CEG-EDA00111-DF -/V5) borrowed from P. Fartouat
  • from 09.06. in lower SCT crate (sbcsct-rcc-05)

-- JohnHill - 27 Mar 2009

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Topic revision: r2 - 2016-06-09 - IskanderIbragimov
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