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The Buffer Control Chip Chip (BCC)

The BCC chip collects and multiplexes the data from the two columns of one hybrid. Its main features are:
  • LVDS buffering
  • 40 MHZ BCO clock multiplier to get a 80 MHz DCLK
  • Config register, with readback
  • ABCN DCLK selectable as 40/80 MHz
  • Multiplexes

BCC configuration

with BCC

The BCC chip implements a clock multiplier for 80 MHz readout and multiplexing of two data streams onto a 80/160 MHz data line (depending on the data clock frequency). It has a 16-bit configuration register which is writable though the command line and remains unaffected by a reset through the L1R line. The meaning of each bit is shown below.

  • The BCC receives the BCO, COM and L1R signals in differential mode from the outside world. It extracts the reset and trigger commands from L1R and decoded the commands on the COM.
  • All clock signals are derived from the BCO input.
  • The power-on reset disables the chip for 512 cycles of the BCO clock.
  • Each BCC has a hardware address that can be set on the ID0-ID5 inputs.
  • The BCC includes a header in the commands forwarded to the ABCN chips are . The BCC(s) concerned by this header forwards the payload to the ABCNs.
  • It demultiplexes the L1R signal into the reset and trigger signals.

Checking the BCC configuration

bit Meaning Possible values Default value
15 unused - -
14 - - -
13 - - -
12 - - -
11 - - -
10 DCLK enable - -
9 BCO enable - -
8 ACLK enable - -
7 DCLK invert - -
6 BCO - -
5 ACLK invert - -
4 SCLK invert - -
3 80 MHz readout select - -
2 Quad mode select - -
[0,1] Data MUX select source 0,1,2,3 0

Setting delays

mode Quad r80 iSCLK iACLK iBCO iDCLK eACLK eBCO eDCLK sCOL0 sCOL1 CDM b80
0 0 1 1 1 0 0 1 1 1 0 0 0 0

-- SergioGonzalez - 28-Jun-2011

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PDFpdf BCC-Thesis.pdf r1 manage 2197.2 K 2011-06-30 - 13:31 SergioGonzalez  
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Topic revision: r2 - 2011-06-30 - SergioGonzalez
 
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